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    MEMORY DEVICE
    3.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20150054058A1

    公开(公告)日：2015-02-26

    申请号：US14530638

    申请日：2014-10-31

    申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

    发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

    IPC分类号： H01L27/115 ,  H01L29/792

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

    摘要翻译： 提供了一种存储装置，包括：沿第一方向延伸的第一至第三选择线，并且沿与第一方向交叉的第二方向依次布置;多组第一至第三垂直柱，每组选择与第一至第三选择对应的一个组合 并且顺序地布置在第二方向上，将与第一选择线耦合的第三垂直柱连接到与第二选择线耦合的第一垂直柱的第一子互连，连接与第二选择线耦合的第三垂直柱的第二子互连 与第三选择线耦合的第一垂直柱的第二选择线，以及沿第二方向延伸并连接到第一和第二子互连中的对应的位线的位线。

    Memory device
    5.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US09129861B2

    公开(公告)日：2015-09-08

    申请号：US14530638

    申请日：2014-10-31

    申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

    发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

    IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L29/41

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

    摘要翻译： 提供了一种存储装置，包括：沿第一方向延伸的第一至第三选择线，并且沿与第一方向交叉的第二方向依次布置;多组第一至第三垂直柱，每组选择与第一至第三选择对应的一个组合 并且顺序地布置在第二方向上，将与第一选择线耦合的第三垂直柱连接到与第二选择线耦合的第一垂直柱的第一子互连，连接与第二选择线耦合的第三垂直柱的第二子互连 与第三选择线耦合的第一垂直柱的第二选择线，以及沿第二方向延伸并连接到第一和第二子互连中的对应的位线的位线。

    Three-dimensional semiconductor memory device
    7.
    发明授权
    Three-dimensional semiconductor memory device 有权
    三维半导体存储器件

    公开(公告)号：US08530959B2

    公开(公告)日：2013-09-10

    申请号：US13198234

    申请日：2011-08-04

    申请人： Sung-Il Chang ,  Youngwoo Park ,  Kwang Soo Seol

    发明人： Sung-Il Chang ,  Youngwoo Park ,  Kwang Soo Seol

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

    摘要翻译： 提供三维半导体器件。 一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层 的半导体图案以将半导体图案连接到基板。

    Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same
    8.
    发明申请
    Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same 审中-公开
    具有降低存储容量泄漏的易感性的非易失性存储器件及其形成方法

    公开(公告)号：US20110079839A1

    公开(公告)日：2011-04-07

    申请号：US12894863

    申请日：2010-09-30

    申请人： Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

    发明人： Fayrushin Albert ,  Kwang Soo Seol ,  Jaeduk Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    摘要： Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

    摘要翻译： 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

    Light emitting device with three-dimensional structure and fabrication method thereof
    9.
    发明授权
    Light emitting device with three-dimensional structure and fabrication method thereof 失效
    具有三维结构的发光器件及其制造方法

    公开(公告)号：US07888857B2

    公开(公告)日：2011-02-15

    申请号：US11534710

    申请日：2006-09-25

    申请人： Jae Young Choi ,  Byoung Lyong Choi ,  Dong Kee Yi ,  Kwang Soo Seol ,  Seong Jae Choi

    发明人： Jae Young Choi ,  Byoung Lyong Choi ,  Dong Kee Yi ,  Kwang Soo Seol ,  Seong Jae Choi

    IPC分类号： H01J63/04 ,  H01J1/62

    CPC分类号： H01L29/06 ,  B82Y20/00 ,  B82Y30/00 ,  H01L51/502 ,  H01L51/52

    摘要： A three-dimensional light emitting device and a method for fabricating the light emitting device are provided. The light emitting device comprises a substrate and a semiconductor nanoparticle layer wherein the substrate is provided with a plurality of three-dimensional recesses and the surface having the recesses is coated with semiconductor nanoparticles. According to the three-dimensional light emitting device, the formation of the semiconductor nanoparticles on the surface of the recessed substrate increases the light emitting area and enhances the luminescence intensity, leading to an increase in the amount of light emitted from the light emitting device per unit area. Therefore, the three-dimensional light emitting device has the advantage of improved luminescence efficiency.

    摘要翻译： 提供三维发光器件和制造发光器件的方法。 发光器件包括衬底和半导体纳米颗粒层，其中衬底设置有多个三维凹槽，并且具有凹陷的表面涂覆有半导体纳米颗粒。 根据三维发光装置，在凹陷基板的表面上形成半导体纳米颗粒增加发光面积并增强发光强度，导致从发光装置发射的光量增加 单位面积 因此，三维发光装置具有提高发光效率的优点。

    Three-dimensional semiconductor memory device
    10.
    发明授权
    Three-dimensional semiconductor memory device 有权
    三维半导体存储器件

    公开(公告)号：US09111617B2

    公开(公告)日：2015-08-18

    申请号：US13585963

    申请日：2012-08-15

    申请人： Sunil Shim ,  Jang-gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

    发明人： Sunil Shim ,  Jang-gn Yun ,  Jeonghyuk Choi ,  Kwang Soo Seol ,  Jaehoon Jang ,  Jungdal Choi

    IPC分类号： H01L29/78 ,  G11C16/04 ,  H01L27/115

    CPC分类号： G11C16/0466 ,  G11C16/0483 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

    摘要翻译： 提供一种半导体存储器件，包括形成在衬底上的第一和第二单元串，第一和第二单元串共同连接到位线，其中第一和第二单元串中的每一个包括地选择单元，存储单元和 第一和第二串选择单元，其顺序地形成在要连接的基板上，其中，所述接地选择单元连接到地选择线，所述存储单元连接到字线，所述第一串选择单元连接到 第一串选择线，第二串选择单元连接到第二串选择线，并且其中第一单元串的第二串选择单元具有沟道掺杂区。