公开(公告)号：US10043816B2

公开(公告)日：2018-08-07

申请号：US14474867

申请日：2014-09-02

申请人： Kim Taekyung ,  Kwang Soo Seol ,  Seong Soon Cho ,  Sunghoi Hur ,  Jintae Kang

发明人： Kim Taekyung ,  Kwang Soo Seol ,  Seong Soon Cho ,  Sunghoi Hur ,  Jintae Kang

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11519 ,  H01L27/11582 ,  H01L29/792

摘要： A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

公开(公告)号：US09478560B2

公开(公告)日：2016-10-25

申请号：US14940137

申请日：2015-11-12

申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L29/41

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

公开(公告)号：US20150054058A1

公开(公告)日：2015-02-26

申请号：US14530638

申请日：2014-10-31

申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

摘要翻译： 提供了一种存储装置，包括：沿第一方向延伸的第一至第三选择线，并且沿与第一方向交叉的第二方向依次布置;多组第一至第三垂直柱，每组选择与第一至第三选择对应的一个组合 并且顺序地布置在第二方向上，将与第一选择线耦合的第三垂直柱连接到与第二选择线耦合的第一垂直柱的第一子互连，连接与第二选择线耦合的第三垂直柱的第二子互连 与第三选择线耦合的第一垂直柱的第二选择线，以及沿第二方向延伸并连接到第一和第二子互连中的对应的位线的位线。

公开(公告)号：US09269721B2

公开(公告)日：2016-02-23

申请号：US14807879

申请日：2015-07-23

申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

公开(公告)号：US09129861B2

公开(公告)日：2015-09-08

申请号：US14530638

申请日：2014-10-31

申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L29/41

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

摘要翻译： 提供了一种存储装置，包括：沿第一方向延伸的第一至第三选择线，并且沿与第一方向交叉的第二方向依次布置;多组第一至第三垂直柱，每组选择与第一至第三选择对应的一个组合 并且顺序地布置在第二方向上，将与第一选择线耦合的第三垂直柱连接到与第二选择线耦合的第一垂直柱的第一子互连，连接与第二选择线耦合的第三垂直柱的第二子互连 与第三选择线耦合的第一垂直柱的第二选择线，以及沿第二方向延伸并连接到第一和第二子互连中的对应的位线的位线。

公开(公告)号：US08791520B2

公开(公告)日：2014-07-29

申请号：US12986553

申请日：2011-01-07

申请人： Jaeduk Lee ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

发明人： Jaeduk Lee ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/42336 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/7881 ,  H01L29/792

摘要： Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.

摘要翻译： 提供了非易失性存储器件及其形成方法。 隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。 在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。 控制栅极设置在栅极电介质图案上。

公开(公告)号：US08625357B2

公开(公告)日：2014-01-07

申请号：US12917634

申请日：2010-11-02

申请人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

发明人： ByungKyu Cho ,  Kwang Soo Seol ,  Sunghoi Hur ,  Jungdal Choi

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/3418

摘要： Provided is a local self-boosting method of a flash memory device including at least one string having memory cells respectively connected to wordlines. The local self-boosting method includes forming a potential well at a channel of the string and forming potential walls at the potential well to be disposed at both sides of a channel of a selected one of the memory cells. The channel of the selected memory cell is locally limited by the potential walls and boosted when a program voltage is applied to the selected memory cell.

摘要翻译： 提供了一种闪存器件的局部自增强方法，其包括至少一个具有分别连接到字线的存储单元的串。 局部自增强方法包括在串的通道处形成势阱，并在势阱处形成位于所选存储单元的通道两侧的电势壁。 所选择的存储单元的通道在局部受到潜在的壁限制，并且当将程序电压施加到所选择的存储单元时升压。

公开(公告)号：US20110169068A1

公开(公告)日：2011-07-14

申请号：US12986553

申请日：2011-01-07

申请人： JAEDUK LEE ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

发明人： JAEDUK LEE ,  Albert Fayrushin ,  ByungKyu Cho ,  Jungdal Choi ,  Sunghoi Hur ,  Kwang Soo Seol ,  Dohyun Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/7881 ,  H01L29/792

摘要： Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.

摘要翻译： 提供了非易失性存储器件及其形成方法。 隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。 在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。 控制栅极设置在栅极电介质图案上。

公开(公告)号：US20170345907A1

公开(公告)日：2017-11-30

申请号：US15681050

申请日：2017-08-18

申请人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

发明人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC分类号： H01L29/423 ,  H01L29/792 ,  H01L29/51 ,  H01L27/06 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/11582 ,  H01L21/3213

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US09536970B2

公开(公告)日：2017-01-03

申请号：US13072078

申请日：2011-03-25

申请人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

发明人： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Dongchul Yoo ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC分类号： H01L29/792 ,  H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/115 ,  H01L29/51

CPC分类号： H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.