公开(公告)号：US10043816B2

公开(公告)日：2018-08-07

申请号：US14474867

申请日：2014-09-02

申请人： Kim Taekyung ,  Kwang Soo Seol ,  Seong Soon Cho ,  Sunghoi Hur ,  Jintae Kang

发明人： Kim Taekyung ,  Kwang Soo Seol ,  Seong Soon Cho ,  Sunghoi Hur ,  Jintae Kang

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11519 ,  H01L27/11582 ,  H01L29/792

摘要： A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

公开(公告)号：US09478560B2

公开(公告)日：2016-10-25

申请号：US14940137

申请日：2015-11-12

申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L29/41

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

公开(公告)号：US20150054058A1

公开(公告)日：2015-02-26

申请号：US14530638

申请日：2014-10-31

申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

摘要翻译： 提供了一种存储装置，包括：沿第一方向延伸的第一至第三选择线，并且沿与第一方向交叉的第二方向依次布置;多组第一至第三垂直柱，每组选择与第一至第三选择对应的一个组合 并且顺序地布置在第二方向上，将与第一选择线耦合的第三垂直柱连接到与第二选择线耦合的第一垂直柱的第一子互连，连接与第二选择线耦合的第三垂直柱的第二子互连 与第三选择线耦合的第一垂直柱的第二选择线，以及沿第二方向延伸并连接到第一和第二子互连中的对应的位线的位线。

公开(公告)号：US09269721B2

公开(公告)日：2016-02-23

申请号：US14807879

申请日：2015-07-23

申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

公开(公告)号：US09129861B2

公开(公告)日：2015-09-08

申请号：US14530638

申请日：2014-10-31

申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L29/41

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

摘要翻译： 提供了一种存储装置，包括：沿第一方向延伸的第一至第三选择线，并且沿与第一方向交叉的第二方向依次布置;多组第一至第三垂直柱，每组选择与第一至第三选择对应的一个组合 并且顺序地布置在第二方向上，将与第一选择线耦合的第三垂直柱连接到与第二选择线耦合的第一垂直柱的第一子互连，连接与第二选择线耦合的第三垂直柱的第二子互连 与第三选择线耦合的第一垂直柱的第二选择线，以及沿第二方向延伸并连接到第一和第二子互连中的对应的位线的位线。

公开(公告)号：US09287167B2

公开(公告)日：2016-03-15

申请号：US14200002

申请日：2014-03-06

申请人： Kwang Soo Seol ,  Seong Soon Cho ,  Byungjoo Go ,  Hongsoo Kim

发明人： Kwang Soo Seol ,  Seong Soon Cho ,  Byungjoo Go ,  Hongsoo Kim

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L21/76877 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a semiconductor device, comprising: forming a plurality of memory cell strings; coupling an interconnection to at least two of the memory cell strings; and coupling a bitline to the interconnection. The interconnection includes a body extending along a first direction and a protrusion protruding from the body along a second direction.

摘要翻译： 一种制造半导体器件的方法，包括：形成多个存储单元串; 将互连耦合到所述存储单元串中的至少两个; 并将位线耦合到互连。 互连包括沿着第一方向延伸的主体和沿着第二方向从主体突出的突起。

公开(公告)号：US20160343434A1

公开(公告)日：2016-11-24

申请号：US14969843

申请日：2015-12-15

申请人： Joonhee Lee ,  Jiyoung Kim ,  Jintaek Park ,  Seong Soon Cho

发明人： Joonhee Lee ,  Jiyoung Kim ,  Jintaek Park ,  Seong Soon Cho

IPC分类号： G11C13/00

CPC分类号： G11C13/0026 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/24 ,  H01L27/2454 ,  H01L27/2481

摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.

摘要翻译： 提供半导体器件。 半导体器件包括交替栅极和绝缘层的堆叠。 半导体器件包括虚拟单元区域。 半导体器件包括多个位线和多个辅助位线。 多个辅助位线中的一些具有不同的相应长度。 还提供了形成半导体器件的相关方法。

公开(公告)号：US08154104B2

公开(公告)日：2012-04-10

申请号：US12077379

申请日：2008-03-19

申请人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

发明人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

IPC分类号： H01L27/06

CPC分类号： H01L27/1052 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L28/20

摘要： In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.

摘要翻译： 在半导体器件及其制造方法中，半导体器件包括包括第一区域和第二区域的衬底。 至少一个第一栅极结构在第一区域中的衬底上，所述至少一个第一栅极结构包括第一栅极绝缘层和第一栅极绝缘层上的第一栅极电极层。 至少一个隔离结构位于第二区域中的衬底中，隔离结构的顶表面的高度低于衬底的顶表面。 至少一个隔离结构上至少有一个电阻器图案。

公开(公告)号：US20090051008A1

公开(公告)日：2009-02-26

申请号：US12077379

申请日：2008-03-19

申请人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

发明人： Jinhyun Shin ,  Minchul Kim ,  Seong Soon Cho ,  Seungwook Choi

IPC分类号： H01L27/06 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L27/1052 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L28/20

摘要： In a semiconductor device and a method of making the same, the semiconductor device comprises a substrate including a first region and a second region. At least one first gate structure is on the substrate in the first region, the at least one first gate structure including a first gate insulating layer and a first gate electrode layer on the first gate insulating layer. At least one isolating structure is in the substrate in the second region, a top surface of the isolating structure being lower in height than a top surface of the substrate. At least one resistor pattern is on the at least one isolating structure.

摘要翻译： 在半导体器件及其制造方法中，半导体器件包括包括第一区域和第二区域的衬底。 至少一个第一栅极结构在第一区域中的衬底上，所述至少一个第一栅极结构包括第一栅极绝缘层和第一栅极绝缘层上的第一栅极电极层。 至少一个隔离结构位于第二区域中的衬底中，隔离结构的顶表面的高度低于衬底的顶表面。 至少一个隔离结构上至少有一个电阻器图案。

公开(公告)号：US10032791B2

公开(公告)日：2018-07-24

申请号：US15403779

申请日：2017-01-11

申请人： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

发明人： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/42328 ,  H01L29/42344

摘要： A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.