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    CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY
    1.
    发明申请
    CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY 有权
    电路设计检查三维芯片技术

    公开(公告)号：US20120304138A1

    公开(公告)日：2012-11-29

    申请号：US13113421

    申请日：2011-05-23

    申请人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    发明人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.

    摘要翻译： 一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。 通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。 转换电路设计可以通过标准验证检查进行处理。 该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。 检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。 如果相应的设计单元对应于镜像侧，则设计单元被镜像。 然后所有镜像单元格以正确的顺序与未设计的设计单元合并。 合并设计通过标准验证检查进行处理。 该工具还可以为两个相邻的芯片创建终端金属摘要。 其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

    Enhanced electromigration resistance in TSV structure and design
    2.
    发明授权
    Enhanced electromigration resistance in TSV structure and design 有权
    TSV结构和设计中增强的电迁移阻力

    公开(公告)号：US08288270B2

    公开(公告)日：2012-10-16

    申请号：US13397004

    申请日：2012-02-15

    申请人： Mukta G Farooq ,  John A Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

    发明人： Mukta G Farooq ,  John A Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

    摘要翻译： 这些实施例提供了一种用于减少包含硅通孔（TSV）的电路中的电迁移的方法以及用于TSV的所得新颖结构。 通过半导体衬底形成TSV。 TSV的第一端连接到半导体衬底的器件侧上的第一金属化层。 TSV的第二端连接到半导体衬底的研磨侧的第二金属化层。 在TSV的第一端和第一金属化层的交叉点的TSV的第一端上形成第一平坦边缘。 在TSV的第二端和第二金属化层的交叉点的TSV的第二端上形成第二平坦边缘。 在第一端的顶部放置金属接触网格，金属覆盖率低于百分之八十。

    ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN
    4.
    发明申请
    ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN 有权
    TSV结构和设计中的增强电阻率

    公开(公告)号：US20120199983A1

    公开(公告)日：2012-08-09

    申请号：US13397004

    申请日：2012-02-15

    申请人： Mukta G. Farooq ,  John A. Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

    发明人： Mukta G. Farooq ,  John A. Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

    摘要翻译： 这些实施例提供了一种用于减少包含硅通孔（TSV）的电路中的电迁移的方法以及用于TSV的所得新颖结构。 通过半导体衬底形成TSV。 TSV的第一端连接到半导体衬底的器件侧上的第一金属化层。 TSV的第二端连接到半导体衬底的研磨侧的第二金属化层。 在TSV的第一端和第一金属化层的交叉点的TSV的第一端上形成第一平坦边缘。 在TSV的第二端和第二金属化层的交叉点的TSV的第二端上形成第二平坦边缘。 在第一端的顶部放置金属接触网格，金属覆盖率低于百分之八十。

    Circuit design checking for three dimensional chip technology
    7.
    发明授权
    Circuit design checking for three dimensional chip technology 有权
    电路设计检查三维芯片技术

    公开(公告)号：US08386977B2

    公开(公告)日：2013-02-26

    申请号：US13113421

    申请日：2011-05-23

    申请人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    发明人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5081

    摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.

    摘要翻译： 一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。 通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。 转换电路设计可以通过标准验证检查进行处理。 该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。 检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。 如果相应的设计单元对应于镜像侧，则设计单元被镜像。 然后所有镜像单元格以正确的顺序与未设计的设计单元合并。 合并设计通过标准验证检查进行处理。 该工具还可以为两个相邻的芯片创建终端金属摘要。 其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。