公开(公告)号：US08786059B2

公开(公告)日：2014-07-22

申请号：US13468223

申请日：2012-05-10

申请人： Alexandre Blander ,  Jon A Casey ,  Timothy H Daubenspeck ,  Ian D Melville ,  Jennifer V Muncy ,  Marie-Claude Paquet

发明人： Alexandre Blander ,  Jon A Casey ,  Timothy H Daubenspeck ,  Ian D Melville ,  Jennifer V Muncy ,  Marie-Claude Paquet

IPC分类号： H01L23/58

CPC分类号： H01L23/295 ,  H01L21/563 ,  H01L23/3142 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.

摘要翻译： 公开了一种其制造方法。 该结构包括具有悬浮在其中的固体的有机钝化层。 优选蚀刻去除一部分有机材料并暴露这些固体的部分产生增强的表面粗糙度，这提供了关于该钝化层与包装底部填充材料的粘附性的显着优点。

公开(公告)号：US08120175B2

公开(公告)日：2012-02-21

申请号：US11947832

申请日：2007-11-30

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

IPC分类号： H01L23/48

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

摘要翻译： 一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。 因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分 最接近芯片表面。 载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。 在开口的底部使用焊料将导电柱连接到开口的底部。 屏障防止焊料接触由屏障保护的导电柱的部分。

公开(公告)号：US20090243098A1

公开(公告)日：2009-10-01

申请号：US12054713

申请日：2008-03-25

申请人： Mukta G. Farooq ,  Robert Hannon ,  Emily R. Kinser ,  Ian D. Melville

发明人： Mukta G. Farooq ,  Robert Hannon ,  Emily R. Kinser ,  Ian D. Melville

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.

摘要翻译： 第一金属扩散阻挡层形成在暴露在钝化层的开口中的最后一级金属板上。 任选地，在第一金属扩散阻挡层上形成金属粘附促进层。 在金属粘合促进层上形成元素金属导电层，其提供高导电性结构，其由于材料的导电性高于或高于上述层而导致电流均匀分布。 形成第二金属扩散阻挡层和润湿促进层的叠层，其上结合有C4球。 元素金属导电层将电流均匀分布在下焊管冶金结构内，从而在C4球中引起更均匀的电流分布，提高C4球的电迁移阻力。

公开(公告)号：US20090140420A1

公开(公告)日：2009-06-04

申请号：US11947832

申请日：2007-11-30

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

摘要翻译： 一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。 因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分 最接近芯片表面。 载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。 在开口的底部使用焊料将导电柱连接到开口的底部。 屏障防止焊料接触由屏障保护的导电柱的部分。

公开(公告)号：US20090032974A1

公开(公告)日：2009-02-05

申请号：US11831026

申请日：2007-07-31

申请人： Mukta G. Farooq ,  Robert Hannon ,  Dae-Young Jung ,  Ian D. Melville

发明人： Mukta G. Farooq ,  Robert Hannon ,  Dae-Young Jung ,  Ian D. Melville

IPC分类号： H01L21/00 ,  H01L23/528

CPC分类号： H01L21/563 ,  H01L24/32 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/29036 ,  H01L2224/321 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/83379 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05599

摘要： A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.

摘要翻译： 组装微电子倒装芯片布置的方法包括将具有限定长度的芯片附接到支撑衬底，其中芯片在支撑衬底上形成具有限定长度的芯片阴影线，在外部形成第一非可湿润区域 在芯片阴影线外部的支撑基板的一部分上形成第二不可润湿区域，在芯片上填充并形成圆角，其中圆角不延伸超过芯片阴影线，以及 硬化底部填充物，包括圆角。

公开(公告)号：US20080274608A1

公开(公告)日：2008-11-06

申请号：US12174074

申请日：2008-07-16

申请人： Ian D. Melville ,  Mukta G. Farooq ,  Dae Young Jung

发明人： Ian D. Melville ,  Mukta G. Farooq ,  Dae Young Jung

IPC分类号： H01L21/768

CPC分类号： H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

摘要： The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced.

摘要翻译： 本发明提供了半导体集成电路和芯片封装之间的接合焊盘结构，其具有增强的抗断裂性和改进的可靠性。 在粘结结构中使用的材料之间的温度膨胀系数（CTE）的不匹配会对其造成应力和剪切，这可能导致后端介质堆叠中的断裂，并导致包装的可靠性问题。 通过设置通过多个金属通孔连接到接合焊盘的多个金属焊盘，增强了接合焊盘和后端电介质叠层之间的粘附力。

公开(公告)号：US20080111250A1

公开(公告)日：2008-05-15

申请号：US11559130

申请日：2006-11-13

申请人： Ian D. Melville ,  Mukta G. Farooq ,  Dae Young Jung

发明人： Ian D. Melville ,  Mukta G. Farooq ,  Dae Young Jung

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

摘要： The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced.

公开(公告)号：US20130020682A1

公开(公告)日：2013-01-24

申请号：US13187917

申请日：2011-07-21

申请人： Jennifer C. Clark ,  Emily R. Kinser ,  Ian D. Melville ,  Candace A. Sullivan

发明人： Jennifer C. Clark ,  Emily R. Kinser ,  Ian D. Melville ,  Candace A. Sullivan

IPC分类号： H01L29/06 ,  H01L21/306 ,  H01L21/311 ,  H01L29/12

CPC分类号： H01L21/311 ,  H01L21/0209 ,  H01L21/30604 ,  H01L21/30608 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00

摘要： A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.

摘要翻译： 晶片和制造方法包括包括用于制造半导体器件的衬底的基底结构。 底座结构包括形成半导体器件的前侧和与前侧相对的后侧。 在基底结构的背面形成一个集成层，其中包括被配置为改变相对于基底结构的蚀刻选择性的杂质，使得集成层可选择性地从基底结构移除，以消除半导体器件的制造过程中产生的缺陷。

公开(公告)号：US20120161300A1

公开(公告)日：2012-06-28

申请号：US13409643

申请日：2012-03-01

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

IPC分类号： H01L23/552

CPC分类号： H01L23/5329 ,  H01L23/556 ,  H01L2924/0002 ,  Y10S438/958 ,  Y10S438/967 ,  H01L2924/00

摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。

公开(公告)号：US20120135564A1

公开(公告)日：2012-05-31

申请号：US13361057

申请日：2012-01-30

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca

IPC分类号： H01L21/60

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.

摘要翻译： 一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。 因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分 最接近芯片表面。 载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。 在开口的底部使用焊料将导电柱连接到开口的底部。 屏障防止焊料接触由屏障保护的导电柱的部分。