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    ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN
    3.
    发明申请
    ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN 有权
    TSV结构和设计中的增强电阻率

    公开(公告)号：US20120199983A1

    公开(公告)日：2012-08-09

    申请号：US13397004

    申请日：2012-02-15

    Applicant: Mukta G. Farooq ,  John A. Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

    Inventor： Mukta G. Farooq ,  John A. Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

    Abstract translation: 这些实施例提供了一种用于减少包含硅通孔（TSV）的电路中的电迁移的方法以及用于TSV的所得新颖结构。 通过半导体衬底形成TSV。 TSV的第一端连接到半导体衬底的器件侧上的第一金属化层。 TSV的第二端连接到半导体衬底的研磨侧的第二金属化层。 在TSV的第一端和第一金属化层的交叉点的TSV的第一端上形成第一平坦边缘。 在TSV的第二端和第二金属化层的交叉点的TSV的第二端上形成第二平坦边缘。 在第一端的顶部放置金属接触网格，金属覆盖率低于百分之八十。

    Structure for charge dissipation during fabrication of integrated circuits and isolation thereof
    4.
    发明授权
    Structure for charge dissipation during fabrication of integrated circuits and isolation thereof 有权
    集成电路制造过程中电荷耗散的结构及其分离

    公开(公告)号：US08110875B2

    公开(公告)日：2012-02-07

    申请号：US12166362

    申请日：2008-07-02

    Applicant: John Joseph Ellis-Monaghan ,  Jeffrey Peter Gambino ,  Timothy Dooling Sullivan ,  Steven Howard Voldman

    Inventor： John Joseph Ellis-Monaghan ,  Jeffrey Peter Gambino ,  Timothy Dooling Sullivan ,  Steven Howard Voldman

    IPC: H01L23/62

    CPC classification number: H01L27/0248 ,  Y10S438/926

    Abstract: A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

    Abstract translation: 用于在集成电路制造期间耗散电荷的结构。 该结构包括：半导体衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

    INTEGRATION CIRCUITS FOR REDUCING ELECTROMIGRATION EFFECT
    5.
    发明申请
    INTEGRATION CIRCUITS FOR REDUCING ELECTROMIGRATION EFFECT 失效
    用于降低电气效应的集成电路

    公开(公告)号：US20080203495A1

    公开(公告)日：2008-08-28

    申请号：US11680081

    申请日：2007-02-28

    Applicant: Anthony Kendall Stamper ,  Timothy Dooling Sullivan ,  Ping-Chuan Wang

    Inventor： Anthony Kendall Stamper ,  Timothy Dooling Sullivan ,  Ping-Chuan Wang

    IPC: H01L29/772

    CPC classification number: H01L23/5221 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.

    Abstract translation: 一种降低电迁移效应的集成电路。 IC包括具有第一和第二源/漏区的衬底和功率晶体管。 IC还包括第一，第二和第三导电线段，其直接在第一源极/漏极区域的上方，以及（ii）分别通过第一接触区域和第二接触区域电耦合到第一源极/漏极区域。 第一和第二导电线段（i）驻留在集成电路的第一互连层中，并且（ii）沿参考方向延伸。 IC还包括导电线，其是（i）直接在第一源极/漏极区域上方，（ii）分别通过第一通孔和第二通孔电耦合到第一和第二导电线段，（iii）驻留 在集成电路的第二互连层中，以及（iv）在参考方向上延伸。

    Enhanced electromigration resistance in TSV structure and design
    6.
    发明授权
    Enhanced electromigration resistance in TSV structure and design 有权
    TSV结构和设计中增强的电迁移阻力

    公开(公告)号：US08288270B2

    公开(公告)日：2012-10-16

    申请号：US13397004

    申请日：2012-02-15

    Applicant: Mukta G Farooq ,  John A Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

    Inventor： Mukta G Farooq ,  John A Griesemer ,  Gary LaFontant ,  William Francis Landers ,  Timothy Dooling Sullivan

    IPC: H01L21/4763

    CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.

    Abstract translation: 这些实施例提供了一种用于减少包含硅通孔（TSV）的电路中的电迁移的方法以及用于TSV的所得新颖结构。 通过半导体衬底形成TSV。 TSV的第一端连接到半导体衬底的器件侧上的第一金属化层。 TSV的第二端连接到半导体衬底的研磨侧的第二金属化层。 在TSV的第一端和第一金属化层的交叉点的TSV的第一端上形成第一平坦边缘。 在TSV的第二端和第二金属化层的交叉点的TSV的第二端上形成第二平坦边缘。 在第一端的顶部放置金属接触网格，金属覆盖率低于百分之八十。

    Wafer edge conditioning for thinned wafers
    9.
    发明授权
    Wafer edge conditioning for thinned wafers 有权
    用于薄晶片的晶圆边缘调节

    公开(公告)号：US09105465B2

    公开(公告)日：2015-08-11

    申请号：US13053803

    申请日：2011-03-22

    Applicant: Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

    Inventor： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

    IPC: H01L29/02 ,  H01L21/02

    CPC classification number: H01L21/02021

    Abstract: The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.

    Abstract translation: 本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。 提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。 该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。 该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。 有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。

    Optoelectronic memory devices
    10.
    发明授权
    Optoelectronic memory devices 有权
    光电存储器件

    公开(公告)号：US08288747B2

    公开(公告)日：2012-10-16

    申请号：US12842158

    申请日：2010-07-23

    Applicant: Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

    Inventor： Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

    IPC: H01L29/00 ,  H01L47/00

    CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

    Abstract: A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.

    Abstract translation: 一个结构。 该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。 电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。 电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

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