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    Circuit design checking for three dimensional chip technology
    1.
    发明授权
    Circuit design checking for three dimensional chip technology 有权
    电路设计检查三维芯片技术

    公开(公告)号：US08386977B2

    公开(公告)日：2013-02-26

    申请号：US13113421

    申请日：2011-05-23

    申请人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    发明人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5081

    摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.

    摘要翻译： 一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。 通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。 转换电路设计可以通过标准验证检查进行处理。 该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。 检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。 如果相应的设计单元对应于镜像侧，则设计单元被镜像。 然后所有镜像单元格以正确的顺序与未设计的设计单元合并。 合并设计通过标准验证检查进行处理。 该工具还可以为两个相邻的芯片创建终端金属摘要。 其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

    CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY
    2.
    发明申请
    CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY 有权
    电路设计检查三维芯片技术

    公开(公告)号：US20120304138A1

    公开(公告)日：2012-11-29

    申请号：US13113421

    申请日：2011-05-23

    申请人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    发明人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.

    摘要翻译： 一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。 通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。 转换电路设计可以通过标准验证检查进行处理。 该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。 检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。 如果相应的设计单元对应于镜像侧，则设计单元被镜像。 然后所有镜像单元格以正确的顺序与未设计的设计单元合并。 合并设计通过标准验证检查进行处理。 该工具还可以为两个相邻的芯片创建终端金属摘要。 其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

    Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via
    5.
    发明授权
    Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via 有权
    垂直金属绝缘体金属（MIM）电容器，采用栅极叠层，栅极隔离和接触通孔

    公开(公告)号：US08017997B2

    公开(公告)日：2011-09-13

    申请号：US12344697

    申请日：2008-12-29

    申请人： Ramachandra Divakaruni ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Kevin S. Petrarca

    发明人： Ramachandra Divakaruni ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Kevin S. Petrarca

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L28/60 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance.

    摘要翻译： 包括垂直金属 - 绝缘体 - 金属电容器的半导体结构以及包括垂直金属 - 绝缘体 - 金属电容器的半导体结构的制造方法，每个都使用位于隔离层上并形成的虚设金属氧化物半导体场效应晶体管的结构部件 区域位于半导体衬底上。 虚拟金属氧化物场效应晶体管可以与位于包括隔离区域的半导体衬底之上的金属氧化物半导体场效应晶体管同时形成。 金属 - 绝缘体 - 金属电容器使用栅极作为电容器板，均匀厚度的栅极间隔物作为栅极电介质和作为另一个电容器板的接触通孔。 均匀厚度的栅极间隔物可以包括用于增强电容的导体层。 使用单个接触通孔的镜像金属 - 绝缘体 - 金属电容器结构也可用于增强电容。