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    Circuit design checking for three dimensional chip technology
    1.
    发明授权
    Circuit design checking for three dimensional chip technology 有权
    电路设计检查三维芯片技术

    公开(公告)号：US08386977B2

    公开(公告)日：2013-02-26

    申请号：US13113421

    申请日：2011-05-23

    申请人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    发明人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5081

    摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.

    摘要翻译： 一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。 通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。 转换电路设计可以通过标准验证检查进行处理。 该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。 检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。 如果相应的设计单元对应于镜像侧，则设计单元被镜像。 然后所有镜像单元格以正确的顺序与未设计的设计单元合并。 合并设计通过标准验证检查进行处理。 该工具还可以为两个相邻的芯片创建终端金属摘要。 其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

    CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY
    2.
    发明申请
    CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY 有权
    电路设计检查三维芯片技术

    公开(公告)号：US20120304138A1

    公开(公告)日：2012-11-29

    申请号：US13113421

    申请日：2011-05-23

    申请人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    发明人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.

    摘要翻译： 一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。 通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。 转换电路设计可以通过标准验证检查进行处理。 该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。 检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。 如果相应的设计单元对应于镜像侧，则设计单元被镜像。 然后所有镜像单元格以正确的顺序与未设计的设计单元合并。 合并设计通过标准验证检查进行处理。 该工具还可以为两个相邻的芯片创建终端金属摘要。 其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

    Method for forming conductive structures
    8.
    发明授权
    Method for forming conductive structures 有权
    形成导电结构的方法

    公开(公告)号：US07833893B2

    公开(公告)日：2010-11-16

    申请号：US11775257

    申请日：2007-07-10

    申请人： Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Richard Paul Volant

    发明人： Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Richard Paul Volant

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76873 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76865

    摘要： A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.

    摘要翻译： 形成导线方法的方法。 该方法包括在电介质层上形成电介质硬掩模层; 在介电硬掩模层上形成导电硬掩模层; 形成延伸穿过所述导电和介电硬掩模层的沟槽进入所述电介质层; 在导电硬掩模层和沟槽的侧壁和底部上沉积衬里/籽晶层; 用填充材料填充沟槽; 从所述导电硬掩模层的顶表面去除所述衬里/籽晶层; 从沟槽中移除填充材料; 将金属层电镀到导电硬掩模层和衬里/籽晶层的暴露表面上; 并且从电介质硬掩模层去除金属层和导电硬掩模层，使得金属层和衬里/籽晶层的边缘与电介质硬掩模层的顶表面共面。

    METHOD FOR FORMING CONDUCTIVE STRUCTURES
    9.
    发明申请
    METHOD FOR FORMING CONDUCTIVE STRUCTURES 有权
    形成导电结构的方法

    公开(公告)号：US20090017616A1

    公开(公告)日：2009-01-15

    申请号：US11775257

    申请日：2007-07-10

    申请人： Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Richard Paul Volant

    发明人： Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Richard Paul Volant

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76873 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76865

    摘要： A method of forming a method a conductive wire. The method includes forming a dielectric hardmask layer on a dielectric layer; forming an electrically conductive hardmask layer on the dielectric hardmask layer; forming a trench extending through the conductive and dielectric hardmask layers into the dielectric layer; depositing a liner/seed layer on the conductive hardmask layer and the sidewalls and bottom of the trench; filling the trench with a fill material; removing the liner/seed layer from the top surface of the conductive hardmask layer; removing the fill material from the trench; electroplating a metal layer onto exposed surfaces of the conductive hardmask layer and liner/seed layer; and removing the metal layer and the conductive hardmask layer from the dielectric hardmask layer so the metal layer and edges of the liner/seed layer are coplanar with the top surface of the dielectric hardmask layer.

    摘要翻译： 形成导线方法的方法。 该方法包括在电介质层上形成电介质硬掩模层; 在介电硬掩模层上形成导电硬掩模层; 形成延伸穿过所述导电和介电硬掩模层的沟槽进入所述电介质层; 在导电硬掩模层和沟槽的侧壁和底部上沉积衬里/籽晶层; 用填充材料填充沟槽; 从所述导电硬掩模层的顶表面去除所述衬里/籽晶层; 从沟槽中移除填充材料; 将金属层电镀到导电硬掩模层和衬里/籽晶层的暴露表面上; 并且从电介质硬掩模层去除金属层和导电硬掩模层，使得金属层和衬里/籽晶层的边缘与电介质硬掩模层的顶表面共面。