Tray for portable digital radiography cassette
    1.
    发明授权
    Tray for portable digital radiography cassette 有权
    托盘用于便携式数字放射摄影盒

    公开(公告)号:US07909511B2

    公开(公告)日:2011-03-22

    申请号:US12404403

    申请日:2009-03-16

    申请人: John H. Hall

    发明人: John H. Hall

    IPC分类号: H01J31/50

    摘要: An apparatus for digital radiography has a cassette adapted to obtain a digital image of a subject in response to incident radiation when receiving source power through an input power connector and adapted to provide the obtained digital image as output from a first data connector. A support tray is adapted to removably seat the cassette and has a second data connector that releasably engages with the first data connector on the cassette when the cassette is seated in the support tray. A wireless communication circuit in the support tray is energizable to transmit the digital image obtained from first data connector of the cassette to a host processor. A battery in the tray provides source power to at least the wireless communication circuit on the support tray circuitry and the input power connector of the seated cassette.

    摘要翻译: 一种用于数字射线照相术的装置具有适于在通过输入电源连接器接收源功率时响应于入射辐射获得被摄体的数字图像的盒,并适于将获得的数字图像作为第一数据连接器的输出提供。 支撑托盘适于可移除地安置盒子,并且具有第二数据连接器,当盒子位于支撑托盘中时,第二数据连接器可释放地与盒上的第一数据连接器接合。 支持托盘中的无线通信电路可激励以将从盒的第一数据连接器获得的数字图像发送到主机处理器。 托盘中的电池至少提供支撑托盘电路上的无线通信电路和座位盒的输入电源连接器的电源。

    TRAY FOR PORTABLE DIGITAL RADIOGRAPHY CASSETTE
    2.
    发明申请
    TRAY FOR PORTABLE DIGITAL RADIOGRAPHY CASSETTE 有权
    便携式数字放映机托盘

    公开(公告)号:US20100232575A1

    公开(公告)日:2010-09-16

    申请号:US12404403

    申请日:2009-03-16

    申请人: John H. Hall

    发明人: John H. Hall

    IPC分类号: H01J31/50

    摘要: An apparatus for digital radiography has a cassette adapted to obtain a digital image of a subject in response to incident radiation when receiving source power through an input power connector and adapted to provide the obtained digital image as output from a first data connector. A support tray is adapted to removably seat the cassette and has a second data connector that releasably engages with the first data connector on the cassette when the cassette is seated in the support tray. A wireless communication circuit in the support tray is energizable to transmit the digital image obtained from first data connector of the cassette to a host processor. A battery in the tray provides source power to at least the wireless communication circuit on the support tray circuitry and the input power connector of the seated cassette.

    摘要翻译: 一种用于数字射线照相术的装置具有适于在通过输入电源连接器接收源功率时响应于入射辐射获得被摄体的数字图像的盒,并适于将获得的数字图像作为第一数据连接器的输出提供。 支撑托盘适于可移除地安置盒子,并且具有第二数据连接器,当盒子位于支撑托盘中时,第二数据连接器可释放地与盒上的第一数据连接器接合。 支持托盘中的无线通信电路可激励以将从盒的第一数据连接器获得的数字图像发送到主机处理器。 托盘中的电池至少提供支撑托盘电路上的无线通信电路和座位盒的输入电源连接器的电源。

    Conductance modulated integrated transistor structure with low drain
capacitance
    4.
    发明授权
    Conductance modulated integrated transistor structure with low drain capacitance 失效
    具有低漏极电容的电导调制集成晶体管结构

    公开(公告)号:US5164812A

    公开(公告)日:1992-11-17

    申请号:US694435

    申请日:1991-05-01

    申请人: John H. Hall

    发明人: John H. Hall

    IPC分类号: H01L27/07

    CPC分类号: H01L27/0716

    摘要: Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each transistor including a source region and a drain region with a gate contact positioned over a channel region therebetween, an ohmic contact to the source regions, and a Schottky contact or PN rectifying junction to each of the drain regions. The dopant concentration of the drain regions is sufficiently low to prevent the Schottky contacts from forming ohmic contacts with the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two Schottky contacts are interconnected as the output of the device. The operation of the device is such that the lightly doped drain regions act as bases of bipolar transistors, with the emitters formed by the Schottky and PN diodes. Majority carriers injected by the Schottky diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device. Speed of operation in enhanced by providing dielectric material between the drain regions and the substrate.

    摘要翻译: 公开了具有增加的电导和操作速度的集成晶体管结构,包括互补的绝缘栅场效应晶体管对,每个晶体管包括源极区和漏极区,栅极接触位于它们之间的沟道区之上,与源的欧姆接触 区域,以及到每个漏极区域的肖特基接触或PN整流结。 漏极区域的掺杂剂浓度足够低,以防止肖特基接触与漏极区域形成欧姆接触。 两个晶体管的栅极互连并用作输入端子,并且两个肖特基触点作为器件的输出互连。 器件的操作使得轻掺杂漏极区域充当双极晶体管的基极,其中由肖特基和PN二极管形成的发射极。 由肖特基二极管注入的多数载流子调制沟道区,从而降低其电阻率并增加器件的跨导,而不增加器件的物理尺寸或电容,从而提高器件的速度。 通过在漏极区域和衬底之间提供介电材料来增强操作速度。

    Clocked CBICMOS integrated transistor structure
    5.
    发明授权
    Clocked CBICMOS integrated transistor structure 失效
    时钟CBICMOS集成晶体管结构

    公开(公告)号:US5119160A

    公开(公告)日:1992-06-02

    申请号:US614938

    申请日:1990-11-19

    申请人: John H. Hall

    发明人: John H. Hall

    IPC分类号: H01L27/07

    CPC分类号: H01L27/0716

    摘要: Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each transistor including a source region and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a diode junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two diode junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. The transconductors of the MOS transistors is multiplied by the beta of the bipolar transistors. The ohmic contacts to the drain regions can be interconnected, and the low on resistance of the opposite polarity drive transistor extracts any excess stored charge in the drain region. Two clocked transistors interconnect the complementary insulated gate field-effect transistor pair to voltage potentials whereby operation of the integrated transistor structure is clocked.

    摘要翻译: 公开了一种具有增加的电导和运行速度的集成晶体管结构,包括互补绝缘栅场效应晶体管对,每个晶体管包括源极区和漏极区,栅极接触位于其间,与源极和漏极区的欧姆接触,以及 二极管接点连接到每个漏极区域。 两个晶体管的栅极互连并用作输入端,并且两个二极管结触点作为器件的输出互连。 器件的操作使得轻掺杂漏极区域充当双极晶体管的基极,由p-n结二极管形成发射极。 MOS晶体管的跨导体乘以双极晶体管的β。 与漏极区域的欧姆接触可以互连,并且相反极性驱动晶体管的低导通电阻提取漏极区域中的任何多余的存储电荷。 两个时钟晶体管将互补的绝缘栅场效应晶体管对互连到电压电位,由此集成晶体管结构的操作被计时。

    Double diffused CMOS with Schottky to drain contacts
    6.
    发明授权
    Double diffused CMOS with Schottky to drain contacts 失效
    双扩散CMOS与肖特基到漏极触点

    公开(公告)号:US5061981A

    公开(公告)日:1991-10-29

    申请号:US500227

    申请日:1990-03-27

    申请人: John H. Hall

    发明人: John H. Hall

    摘要: This is an invention for a complementary transistor pair which includes an n-channel double-diffused-metal-oxide-semiconductor transistor having a source, a drain and an insulated gate. A Schottky barrier junction diode is formed to the drain of the n-channel transistor. The transistor pair also includes a p-channel double-diffused-metal-oxide-semiconductor transistor which also has a source, a drain and an insulated gate. A second Schottky barrier junction diode is formed to the drain of the p-channel transistor. The two Schottky diodes are electrically coupled to one another.

    摘要翻译: 这是用于互补晶体管对的发明,其包括具有源极,漏极和绝缘栅极的n沟道双扩散金属氧化物半导体晶体管。 肖特基势垒结二极管形成在n沟道晶体管的漏极上。 晶体管对还包括还具有源极,漏极和绝缘栅极的p沟道双扩散金属氧化物半导体晶体管。 第二肖特基势垒结二极管形成于p沟道晶体管的漏极。 两个肖特基二极管彼此电耦合。

    Method of forming localized epitaxy and devices formed therein
    7.
    发明授权
    Method of forming localized epitaxy and devices formed therein 失效
    形成局部外延的方法及其中形成的器件

    公开(公告)号:US4566914A

    公开(公告)日:1986-01-28

    申请号:US494124

    申请日:1983-05-13

    申请人: John H. Hall

    发明人: John H. Hall

    摘要: An integrated circuit structure for isolating circuit structures in closely packed integrated circuits, and a method for making the same. The isolation structure includes a semiconductor body having a surface, an insulatory layer on the surface having an aperture and an offset adjacent to the aperture, the aperture and offset being filled with epitaxial semiconductor material, at least a portion of the epitaxial material being single crystal semiconductor, said structure being used for the fabrication of standard semiconductor devices. The method uses conventional processing techniques that require a minimum of additional cost over prior art, and yet provide a high degree of device isolation and density.

    摘要翻译: 一种用于隔离紧凑型集成电路中的电路结构的集成电路结构及其制造方法。 隔离结构包括具有表面的半导体本体,表面上的隔离层具有孔径和邻近孔径的偏移,孔和偏移物被外延半导体材料填充,外延材料的至少一部分为单晶 半导体,所述结构用于制造标准半导体器件。 该方法使用与现有技术相比需要最小额外成本的常规处理技术,并且还提供高度的器件隔离和密度。

    Separable means for excluding oversized slender objects
    8.
    发明授权
    Separable means for excluding oversized slender objects 失效
    可分离的手段,用于排除超大的细长物体

    公开(公告)号:US4367601A

    公开(公告)日:1983-01-11

    申请号:US232862

    申请日:1981-02-09

    IPC分类号: B03B11/00 E02F3/92 E02F3/94

    CPC分类号: E02F3/94 B03B11/00 E02F3/92

    摘要: For screening oversized objects and especially long slender particles wherein the long dimension of the particle is aligned in the direction of flow through a fluid-flow conduit, there is provided a screen comprising a pair of opposing corrugated surfaces, the folds or corrugations on the opposing surfaces being substantially parallel, and separated by a distance, and having a wave length, determined by the size particle to be screened. Preferably, the corrugated surfaces are formed as two sets of a plurality of corrugated plates inserted within and extending along the direction of fluid-flow in a conduit, the sets being relatively movable between a position where the two sets are interleaved, and a position where the two are separated.

    摘要翻译: 为了筛选尺寸过大的物体,特别是长度细长的颗粒,其中颗粒的长尺寸沿着流过流体导管的流动方向排列,提供了一个包括一对相对的波纹表面的筛网,相对的折叠或波纹 表面基本上平行,并且分开一段距离,并且具有由待筛选的尺寸颗粒确定的波长。 优选地,波纹状表面形成为插入管道中的流体流动方向并沿其延伸的两组多个波纹板,所述多个波纹板在两组交错的位置之间可相对移动, 两者分开。

    High temperature refractory metal contact assembly and multiple layer
interconnect structure
    9.
    发明授权
    High temperature refractory metal contact assembly and multiple layer interconnect structure 失效
    高温耐火金属接触组件和多层互连结构

    公开(公告)号:US4152823A

    公开(公告)日:1979-05-08

    申请号:US791798

    申请日:1977-04-28

    申请人: John H. Hall

    发明人: John H. Hall

    摘要: A multi-layer integrated semiconductor circuit interconnection structure with a first layer formed of a refractory metal sandwich including outer layers of silicon and a core of refractory metal providing a high temperature low ohmic contact assembly, an insulating layer formed on the first layer, and a patterned metal layer formed on the insulating layer to interconnect with the refractory layer and semiconductor device to provide an integrated circuit assembly.

    摘要翻译: 一种多层集成半导体电路互连结构,其具有由难熔金属夹层构成的第一层,所述第一层包括硅的外层和提供高温低欧姆接触组件的难熔金属芯,形成在第一层上的绝缘层, 形成在绝缘层上以与耐火层和半导体器件互连以提供集成电路组件的图案化金属层。

    High temperature refractory metal contact assembly and multiple layer
interconnect structure
    10.
    发明授权
    High temperature refractory metal contact assembly and multiple layer interconnect structure 失效
    高温耐火金属接触组件和多层互连结构

    公开(公告)号:US4042953A

    公开(公告)日:1977-08-16

    申请号:US585612

    申请日:1975-06-10

    申请人: John H. Hall

    发明人: John H. Hall

    摘要: A multi-layer integrated semiconductor circuit interconnection structure with a first layer formed of a refractory metal sandwich including outer layers of silicon and a core of refractory metal providing a high temperature low ohmic contact assembly, an insulating layer formed on the first layer, and a patterned metal layer formed on the insulating layer to interconnect with the refractory layer and semiconductor device to provide an integrated circuit assembly.

    摘要翻译: 一种多层集成半导体电路互连结构,其具有由难熔金属夹层构成的第一层,所述第一层包括硅的外层和提供高温低欧姆接触组件的难熔金属芯,形成在第一层上的绝缘层, 形成在绝缘层上以与耐火层和半导体器件互连以提供集成电路组件的图案化金属层。