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    Compound modulated integrated transistor structure with reduced bipolar switch back effect
    1.
    发明授权
    Compound modulated integrated transistor structure with reduced bipolar switch back effect 失效
    复合调制集成晶体管结构具有降低的双极开关反效应

    公开(公告)号：US5567969A

    公开(公告)日：1996-10-22

    申请号：US425173

    申请日：1995-04-20

    申请人： John H. Hall

    发明人： John H. Hall

    IPC分类号： H01L27/07 ,  H01L29/10 ,  H01L29/167 ,  H01L29/76 ,  H01L27/095 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/1087 ,  H01L27/0716 ,  H01L29/167

    摘要： Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field effect transistor pair, each including a source and a drain region with a gate contact positioned therebetween, ohmic contacts to the sources, and a rectifying junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two rectifying contacts are interconnected as the output of the device. The structure includes a semiconductor substrate having slow diffusant dopants therein or implanted metal ions of cobalt, molybdenum, or tungsten. The structure further includes an epitaxial semiconductor layer with resistance on the order of 0.5 to 1.0 ohm cm and a thickness of 1.5 to 5.0 .mu.m. The device regions for the field effect transistor pair are formed in the epitaxial semiconductor layer. Current from a positive voltage source is applied through the substrate to the source of a P-channel field effect transistor, thereby reducing switch back effect.

    摘要翻译： 公开了具有增加的电导和操作速度的集成晶体管结构，包括互补绝缘栅场效应晶体管对，每个包括源极和漏极区域，栅极接触位于它们之间，与源极的欧姆接触以及与每个源极的整流结接点 的漏极区域。 两个晶体管的栅极互连并用作输入端，并且两个整流触点作为器件的输出互连。 该结构包括其中具有缓慢扩散掺杂剂的半导体衬底或钴，钼或钨的注入的金属离子。 该结构还包括具有0.5至1.0欧姆厘米数量级和1.5至5.0μm厚度的电阻的外延半导体层。 用于场效应晶体管对的器件区域形成在外延半导体层中。 来自正电压源的电流通过衬底施加到P沟道场效应晶体管的源极，从而减少开关回复效应。

    Intergrated field effect transistor device for high power and voltage amplification of RF signals
    3.
    发明授权
    Intergrated field effect transistor device for high power and voltage amplification of RF signals 失效
    集成场效应晶体管器件用于RF信号的高功率和电压放大

    公开(公告)号：US06037618A

    公开(公告)日：2000-03-14

    申请号：US24821

    申请日：1998-02-17

    申请人： John H. Hall ,  J. Kirkwood H. Rough

    发明人： John H. Hall ,  J. Kirkwood H. Rough

    IPC分类号： H01L27/088 ,  H01L29/808 ,  H01L29/80 ,  H01L31/112

    CPC分类号： H01L29/8086 ,  H01L27/088 ,  H01L29/8083

    摘要： An integrated transistor device operates with a linear triode vacuum tube like characteristic with a very low output impedance and a large interaction between the gate and drain potentials. The drain current of a first transistor is connected directly to the source of a second transistor which has a low input impedance matching the output impedance of the first transistor. The gate of the second transistor is held at a positive potential and functions to provide isolation of the varying drain signal from the drain of the first transistor and to provide a high impedance at the output terminal. This device structure provides high input impedance, high current gain, high output impedance and a linear operating characteristic.

    摘要翻译： 集成晶体管器件采用线性三极管真空管工作，具有非常低的输出阻抗特性，栅极和漏极之间的相互作用大。 第一晶体管的漏极电流直接连接到具有与第一晶体管的输出阻抗匹配的低输入阻抗的第二晶体管的源极。 第二晶体管的栅极保持在正电位，并且用于提供来自第一晶体管的漏极的变化的漏极信号的隔离并且在输出端子处提供高阻抗。 该器件结构提供高输入阻抗，高电流增益，高输出阻抗和线性工作特性。

    Compound modulated integrated transistor structure
    4.
    发明授权
    Compound modulated integrated transistor structure 失效
    复合调制集成晶体管结构

    公开(公告)号：US5021858A

    公开(公告)日：1991-06-04

    申请号：US528950

    申请日：1990-05-25

    申请人： John H. Hall

    发明人： John H. Hall

    IPC分类号： H01L27/07 ,  H01L27/092

    CPC分类号： H01L27/0716 ,  H01L27/0928

    摘要： Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a p-n junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two p-n junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. Minority carriers injected by the diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device. The ohmic contacts to the drain regions are interconnected, and the low on resistance of the opposite polarity drive transistor extracts any excess stored charge in the drain region.

    摘要翻译： 公开了具有增加的电导和操作速度的集成晶体管结构，包括互补绝缘栅场效应晶体管对，每个包括源极和漏极区域，栅极接触位于它们之间，与源极和漏极区域的欧姆接触以及pn结 接触每个漏区。 两个晶体管的栅极互连并用作输入端，并且两个p-n结触点作为器件的输出互连。 器件的操作使得轻掺杂漏极区域充当双极晶体管的基极，由p-n结二极管形成发射极。 由二极管注入的少数载流子调制沟道区，从而降低其电阻率并增加器件的跨导，而不增加器件的物理尺寸或电容，从而提高器件的速度。 与漏极区域的欧姆接触互连，并且相反极性驱动晶体管的低导通电阻提取漏极区域中的任何多余的存储电荷。

    Apparatus and method for storage phoshor erase
    7.
    发明授权
    Apparatus and method for storage phoshor erase 有权
    用于存储光致擦除的装置和方法

    公开(公告)号：US07087918B2

    公开(公告)日：2006-08-08

    申请号：US10814355

    申请日：2004-03-31

    申请人： John H. Hall

    发明人： John H. Hall

    IPC分类号： G01N23/04

    CPC分类号： G03B42/08

    摘要： An apparatus and method for removing stored energy from a storage phosphor screen in which a radiation image was recorded and then read by collecting stimulated emission from the phosphor sheet. The phosphor sheet is transported along a path in a first direction at a first speed into an erase area having at least one erasing light source. A portion of the phosphor sheet disposed within the erase area is exposed to the light source to affect erasure of the radiation image on the exposed portion of the phosphor sheet. Transport of the phosphor sheet is stopped when the trailing edge of the phosphor sheet enters the erase area and the phosphor sheet dwells within the erase area for a predetermined time period. The phosphor sheet is then transported along the path in a second direction at a second speed, and then transported along the path in the second direction at a third speed when the leading edge exits the erase area.

    摘要翻译： 一种用于从存储荧光屏中去除存储的能量的设备和方法，其中记录了放射线图像，然后通过从磷光体片中收集受激发射来读取。 荧光体片沿着第一方向的路径以第一速度传送到具有至少一个擦除光源的擦除区域。 设置在擦除区域内的荧光体片的一部分暴露于光源，以影响荧光片的曝光部分上的放射线图像的擦除。 当荧光体片的后缘进入擦除区域并且荧光体片材在擦除区域内停留预定时间段时，磷光体片的传送停止。 然后以第二速度沿着第二方向沿着路径传送磷光体片，然后当前缘离开擦除区域时以第三速度沿第二方向沿着路径传送。

    Low voltage compound modulated integrated transistor structure
    8.
    发明授权
    Low voltage compound modulated integrated transistor structure 失效
    低压复合调制集成晶体管结构

    公开(公告)号：US5365100A

    公开(公告)日：1994-11-15

    申请号：US114012

    申请日：1993-08-30

    申请人： John H. Hall

    发明人： John H. Hall

    IPC分类号： H01L27/07 ,  H01L27/092 ,  H01L29/70 ,  H01L29/80 ,  H01L29/91

    CPC分类号： H01L27/092 ,  H01L27/0716

    摘要： Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a p-n junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two p-n junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. Minority carriers injected by the diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device. Second p-n junction contacts to the drain regions are interconnected, and form auxiliary bipolar transistors in the drain regions to extract charge stored in the main transistor collector to base junction and increasing switching speed in the turn off direction. In turn on, the second p-n junction holds the base away from ground thereby increasing turn on speed.

    摘要翻译： 公开了具有增加的电导和操作速度的集成晶体管结构，包括互补绝缘栅场效应晶体管对，每个包括源极和漏极区域，栅极接触位于它们之间，与源极和漏极区域的欧姆接触以及pn结 接触每个漏区。 两个晶体管的栅极互连并用作输入端，并且两个p-n结触点作为器件的输出互连。 器件的操作使得轻掺杂漏极区域充当双极晶体管的基极，由p-n结二极管形成发射极。 由二极管注入的少数载流子调制沟道区，从而降低其电阻率并增加器件的跨导，而不增加器件的物理尺寸或电容，从而提高器件的速度。 与漏极区域的第二p-n结接点互连，并且在漏极区域中形成辅助双极晶体管，以将存储在主晶体管集电极中的电荷提取到基极结，并提高关断方向上的开关速度。 接着，第二个p-n结将基座保持远离地面，从而增加开启速度。

    Conductance-modulated integrated transistor structure
    9.
    发明授权
    Conductance-modulated integrated transistor structure 失效
    电导调制集成晶体管结构

    公开(公告)号：US4920399A

    公开(公告)日：1990-04-24

    申请号：US418962

    申请日：1989-10-10

    申请人： John H. Hall

    发明人： John H. Hall

    IPC分类号： H01L27/07 ,  H01L27/092

    CPC分类号： H01L27/0927 ,  H01L27/0711

    摘要： Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, an ohmic contact to the source regions, and a Schottky contact to each of the drain regions. The dopant concentration of the drain regions is sufficiently low to prevent the Schottky contact from forming an ohmic contact with the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two Schottky contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the Schottky diodes. Minority and majority carriers injected by the Schottky diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device.

    摘要翻译： 公开了具有增加的电导和操作速度的集成晶体管结构，包括互补绝缘栅场效应晶体管对，每个包括源极和漏极区域，栅极接触位于其间，与源极区域的欧姆接触，以及肖特基接触 每个漏极区域。 漏极区域的掺杂剂浓度足够低以防止肖特基接触与漏极区域形成欧姆接触。 两个晶体管的栅极互连并用作输入端子，并且两个肖特基触点作为器件的输出互连。 器件的操作使得轻掺杂漏极区域用作双极晶体管的基极，其中由肖特基二极管形成发射极。 由肖特基二极管注入的少数和多数载流子调制沟道区，从而降低其电阻率并增加器件的跨导，而不增加器件的物理尺寸或电容，从而提高器件的速度。

    High temperature refractory metal contact assembly and multiple layer interconnect structure
    10.
    发明授权
    High temperature refractory metal contact assembly and multiple layer interconnect structure 失效
    高温耐火金属接触组件和多层互连结构

    公开(公告)号：US4265935A

    公开(公告)日：1981-05-05

    申请号：US14256

    申请日：1979-02-22

    申请人： John H. Hall

    发明人： John H. Hall

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/88

    CPC分类号： H01L23/53257 ,  H01L21/76889 ,  H01L2924/0002 ,  Y10S148/147

    摘要： A multi-layer integrated semiconductor circuit interconnection structure with a first layer formed of a refractory metal sandwich including outer layers of silicon and a core of refractory metal providing a high temperature low ohmic contact assembly, an insulating layer formed on the first layer, and a patterned metal layer formed on the insulating layer to interconnect with the refractory layer and semiconductor device to provide an integrated circuit assembly.

    摘要翻译： 一种多层集成半导体电路互连结构，其具有由难熔金属夹层构成的第一层，所述第一层包括硅的外层和提供高温低欧姆接触组件的难熔金属芯，形成在第一层上的绝缘层， 形成在绝缘层上以与耐火层和半导体器件互连以提供集成电路组件的图案化金属层。