公开(公告)号：US06314495B1

公开(公告)日：2001-11-06

申请号：US09004144

申请日：1998-01-07

申请人： Ravi Kumar Arimilli ,  John Michael Kaiser ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  John Michael Kaiser ,  Derek Edward Williams

IPC分类号： G06F1200

CPC分类号： G06F9/524 ,  G06F12/0831

摘要： The present invention is a method and apparatus for preventing the occurrence of deadlocks from the execution of multiply-initiated multiply-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.

摘要翻译： 本发明是一种用于防止从多次发起的多来源可变延迟系统总线操作的执行中发生死锁的方法和装置。 一般来说，每个窥探者除了按照约定的条件同时给定操作。 换句话说，即使在重试操作时，给定缓存中的监听器也可以接受操作并开始处理。 此外，没有一个主动侦听器释放一个操作，直到所有的主动侦听器都完成了操作。 换句话说，给定操作的执行由窥探者同时开始，同时由每个窥探者完成。 这可以防止乒乓的死锁，因为任何一个缓存都不会在其他任何缓存之前完成操作。

公开(公告)号：US06202131B1

公开(公告)日：2001-03-13

申请号：US09004147

申请日：1998-01-07

申请人： Ravi Kumar Arimilli ,  John Michael Kaiser ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  John Michael Kaiser ,  Derek Edward Williams

IPC分类号： G06F1300

CPC分类号： G06F12/0831

摘要： A method and apparatus for preventing the occurrence of deadlocks from the execution of variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. Execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others. The snoopers initiate operations at the same time based upon a common predefined event and ensure the operations end are finished concurrently when no outstanding retry operations are detected.

摘要翻译： 一种用于防止从可变延迟系统总线操作的执行中发生死锁的方法和装置。 一般来说，每个窥探者除了按照约定的条件同时给定操作。 换句话说，即使在重试操作时，给定缓存中的监听器也可以接受操作并开始处理。 此外，没有一个主动侦听器释放一个操作，直到所有的主动侦听器都完成了操作。 给定操作的执行由窥探者同时开始，同时由每个窥探者完成。 这可以防止乒乓的死锁，因为任何一个缓存都不会在其他任何缓存之前完成操作。 侦听器基于公共预定义事件同时启动操作，并确保在没有检测到未完成的重试操作时同时完成操作结束。

公开(公告)号：US06192453B1

公开(公告)日：2001-02-20

申请号：US09114186

申请日：1998-07-13

申请人： Ravi Kumar Arimilli ,  Derek Edward Williams ,  John Michael Kaiser ()

发明人： Ravi Kumar Arimilli ,  Derek Edward Williams ,  John Michael Kaiser ()

IPC分类号： G06F1342

CPC分类号： G06F12/0831

摘要： A method and apparatus for preventing the occurrence of deadlocks from the execution of unresolvable system bus operations. In general, each snooper speculatively accepts a given operation when it has a snoop buffer available. However, rather than unconditionally processing the operation, the snooper waits to determine if another participant retried the operation due to unavailability of a snoop buffer. If some snooping participant retrys an operation, all snoopers that speculatively accepted an operation for processing abandon said operation. If no snooping participant retrys the operation, sufficient snooping resources were available for all necessary caches to begin processing the operation and the initiator can consider the operation completed. In other words, no operation is processed until all the necessary snooping resources are available to accept the operation. This prevents the system from getting into the ping-pong deadlock. Snoopers can safely assume that each presentation of an operation must be propagated and that no operation will have been fully or partially processed by some other snooper. The operation cannot proceed until all of the available resources are available and once available, the operation is propagated only once by those snooping resources.

摘要翻译： 一种用于防止从不可解决的系统总线操作的执行中发生死锁的方法和装置。 一般来说，每个窥探者在有一个snoop缓冲区可用时推测接受给定的操作。 然而，snooper不是无条件地处理这个操作，而是等待确定另一个参与者是否因侦听缓冲区不可用而重试操作。 如果一些侦听参与者重新开始一个操作，那么推测接受处理操作的所有窥探者都放弃了操作。 如果没有侦听参与者重新启动该操作，则可以使用足够的侦听资源进行所有必要的缓存，开始处理操作，启动器可以考虑完成该操作。 换句话说，在所有必需的窥探资源都可用于接受操作之前，不会处理任何操作。 这样可以防止系统进入乒乓僵死。 侦听器可以安全地假定每个演示的操作必须被传播，并且任何操作都不会被其他侦听器完全或部分地处理。 在所有可用资源可用并且一旦可用之前，该操作将无法继续，该操作仅被这些监听资源传播一次。

公开(公告)号：US6141714A

公开(公告)日：2000-10-31

申请号：US114209

申请日：1998-07-13

申请人： Ravi Kumar Arimilli ,  Derek Edward Williams ,  John Michael Kaiser, deceased

发明人： Ravi Kumar Arimilli ,  Derek Edward Williams ,  John Michael Kaiser, deceased

IPC分类号： G06F9/46 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F9/524 ,  G06F12/0811 ,  G06F12/0831

摘要： A method and apparatus for preventing the occurrence of deadlocks from the execution of unresolvable system bus operations. In general, each snooper speculatively accepts a given operation when it has a snoop buffer available. However, rather than unconditionally processing the operation, the snooper waits to determine if another participant retried the operation due to unavailability of a snoop buffer. If some snooping participant retrys an operation, all snoopers that speculatively accepted an operation for processing abandon said operation. If no snooping participant retrys the operation, sufficient snooping resources were available for all necessary caches to begin processing the operation and the initiator can consider the operation completed. In other words, no operation is processed until all the necessary snooping resources are available to accept the operation. This prevents the system from getting into the ping-pong deadlock. Snoopers can safely assume that each presentation of an operation must be propagated and that no operation will have been fully or partially processed by some other snooper. The operation cannot proceed until all of the available resources are available and once available, the operation is propagated only once by those snooping resources.

摘要翻译： 一种用于防止从不可解决的系统总线操作的执行中发生死锁的方法和装置。 一般来说，每个窥探者在有一个snoop缓冲区可用时推测接受给定的操作。 然而，snooper不是无条件地处理这个操作，而是等待确定另一个参与者是否因侦听缓冲区不可用而重试操作。 如果一些侦听参与者重新开始一个操作，那么推测接受处理操作的所有窥探者都放弃了操作。 如果没有侦听参与者重新启动该操作，则可以使用足够的侦听资源进行所有必要的缓存，开始处理操作，启动器可以考虑完成该操作。 换句话说，在所有必需的窥探资源都可用于接受操作之前，不会处理任何操作。 这样可以防止系统进入乒乓僵死。 侦听器可以安全地假定每个演示的操作必须被传播，并且任何操作都不会被其他侦听器完全或部分地处理。 在所有可用资源可用并且一旦可用之前，该操作将无法继续，该操作仅被这些监听资源传播一次。

公开(公告)号：US6029217A

公开(公告)日：2000-02-22

申请号：US317006

申请日：1994-10-03

申请人： Ravi Kumar Arimilli ,  John Michael Kaiser

发明人： Ravi Kumar Arimilli ,  John Michael Kaiser

IPC分类号： G06F15/16 ,  G06F13/362 ,  G06F13/364 ,  G06F15/177 ,  G06F13/20

CPC分类号： G06F13/364

摘要： A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.

摘要翻译： 排队的仲裁机制将所有排队的处理器总线请求以描述和流水线方式传送到集中式系统控制器/仲裁器。 将这些描述性和流水线总线请求传送到系统控制器允许系统控制器通过对所有所请求的总线操作和流水线适当的总线授权的优先级来优化系统总线利用率。 智能总线请求信息通过编码和串行化技术传输到系统控制器。

公开(公告)号：US5940856A

公开(公告)日：1999-08-17

申请号：US837516

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  John Michael Kaiser ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  John Michael Kaiser ,  Jerry Don Lewis

IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0831

摘要： A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into at least two caches, the caches are marked as containing shared, unmodified copies of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, a given one of the caches transmits a response indicating that the given cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.

摘要翻译： 公开了一种改善与多处理器计算机系统中的读取类型操作相关联的存储器延迟的方法。 在将值（数据或指令）从系统存储器加载到至少两个高速缓存中之后，高速缓存被标记为包含值的未修改的共享副本，并且当请求处理单元发出指示期望读取值的消息时 ，给定的一个高速缓存发送指示给定高速缓存可以输出该值的响应。 该响应响应于来自连接到请求处理单元的互连的高速缓存窥探消息而被发送。 响应由系统逻辑检测并从系统逻辑转发到请求处理单元。 高速缓存然后将该值输出到连接到请求处理单元的互连。 系统内存检测到该消息，并且通常会发送该值，但响应通知存储设备该值将由缓存提供。 由于缓存延迟可能远小于内存延迟，因此可以通过此新协议大大提高读取性能。

公开(公告)号：US5745698A

公开(公告)日：1998-04-28

申请号：US704035

申请日：1996-08-28

申请人： Michael Scott Allen ,  Ravi Kumar Arimilli ,  John Michael Kaiser ,  William Kurt Lewchuk

发明人： Michael Scott Allen ,  Ravi Kumar Arimilli ,  John Michael Kaiser ,  William Kurt Lewchuk

IPC分类号： G06F12/10 ,  G06F13/36 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F13/36

摘要： A method and system are provided for communicating between devices. A signal is output from a first device. In response to the signal, at least one action is initiated by a second device. An indication is output of whether the second device completed the action and of whether operation of the second device is independent of the first device reoutputting the signal.

摘要翻译： 提供了用于在设备之间进行通信的方法和系统。 从第一设备输出信号。 响应该信号，由第二设备发起至少一个动作。 输出第二装置是否完成动作的指示以及第二装置的操作是否独立于重新输出信号的第一装置。

公开(公告)号：US5687327A

公开(公告)日：1997-11-11

申请号：US317007

申请日：1994-10-03

申请人： Ravi Kumar Arimilli ,  John Michael Kaiser ,  William Kurt Lewchuk ,  Michael Scott Allen

发明人： Ravi Kumar Arimilli ,  John Michael Kaiser ,  William Kurt Lewchuk ,  Michael Scott Allen

IPC分类号： G06F13/364 ,  G06F13/36

CPC分类号： G06F13/364

摘要： An efficient multiprocessor address transfer mechanism is utilized within a data processing system including a plurality of bus devices. The present invention places control of the flow of address bus operations within the system controller rather than the bus devices, e.g., a master processor. The system controller issues an address bus grant, in response to an address bus request from a particular bus device, and shortly after that issues another signal notifying the granted bus device that it must now disable the address bus. Furthermore, upon receipt of the signal indicating disablement of the address bus, other bus devices may then snoop, or sample, the address bus.

摘要翻译： 在包括多个总线设备的数据处理系统中利用有效的多处理器地址传送机制。 本发明将地址总线操作的流程控制在系统控制器内而不是总线设备，例如主处理器。 系统控制器响应于来自特定总线设备的地址总线请求发出地址总线许可，并且之后不久发出通知授权总线设备现在必须禁用地址总线的另一个信号。 此外，当接收到指示地址总线的禁用的信号时，其他总线设备然后可以窥探或采样地址总线。

公开(公告)号：US5673413A

公开(公告)日：1997-09-30

申请号：US573092

申请日：1995-12-15

申请人： Sanjay Raghunath Deshpande ,  John Michael Kaiser

发明人： Sanjay Raghunath Deshpande ,  John Michael Kaiser

IPC分类号： G06F12/08 ,  G06F13/42 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F12/16

CPC分类号： G06F12/0813 ,  G06F12/0817

摘要： An information processing system includes a plurality of bus devices coupled to at least one storage device via a bus. A first device (the "requestor") on a bus issues a request to obtain data and coherency information and monitors for the coherency information during a designated coherency response interval. A second device (the "respondant") sends a first signal during the designated coherency response interval indicating that the coherency information will be returned during a second interval, and sends a second signal providing the coherency information to the requestor during the second interval.

摘要翻译： 信息处理系统包括通过总线耦合到至少一个存储设备的多个总线设备。 总线上的第一设备（“请求者”）在指定的一致性响应间隔期间发出获取数据和一致性信息的请求并监视一致性信息。 第二设备（“响应者”）在指定的相关性响应间隔期间发送指示在第二间隔期间返回一致性信息的第一信号，并且在第二间隔期间向请求者发送提供一致性信息的第二信号。

公开(公告)号：US5996049A

公开(公告)日：1999-11-30

申请号：US839548

申请日：1997-04-14

申请人： Ravi Kumar Arimilli ,  John Steven Dodson ,  John Michael Kaiser ,  Jerry Don Lewis

发明人： Ravi Kumar Arimilli ,  John Steven Dodson ,  John Michael Kaiser ,  Jerry Don Lewis

IPC分类号： G06F12/08 ,  G06F12/16

CPC分类号： G06F12/0831

摘要： A method of providing instructions and data values to a processing unit in a multi-processor computer system, by expanding the prior-art MESI cache-coherency protocol to include an additional cache-entry state corresponding to a most recently accessed state. Each cache of the processing units has at least one cache line with a block for storing the instruction or data value, and an indication is provided that a cache line having a block which contains the instruction or data value is in a "recently read" state. Each cache entry has three bits to indicate the current state of the cache entry (one of five possible states). A processing unit which desires to access a shared instruction or data value detects transmission of the indication from the cache having the most recently accessed copy, and the instruction or data value is sourced from this cache. Upon sourcing the instruction or data value, the cache that originally contained the most recently accessed copy thereof changes its indication to indicate that its copy is now shared, and the processing unit which accessed the instruction or data value is thereafter indicated as having the cache containing the copy thereof that was most recently accessed. This protocol allows instructions and data values which are shared among several caches to be sourced directly (intervened) by the cache having the most recently accessed copy, without retrieval from system memory (RAM), significantly improving the processing speed of the computer system.

摘要翻译： 通过扩展现有技术的MESI高速缓存一致性协议以包括对应于最近访问状态的附加高速缓存入口状态，向多处理器计算机系统中的处理单元提供指令和数据值的方法。 处理单元的每个高速缓存具有至少一个具有用于存储指令或数据值的块的高速缓存行，并且提供了具有包含指令或数据值的块的高速缓存行处于“最近读取”状态的指示 。 每个缓存条目有三个位用于指示缓存条目的当前状态（五种可能状态之一）。 期望访问共享指令或数据值的处理单元检测来自具有最近访问的副本的高速缓存的指示的传输，并且指令或数据值来自该高速缓存。 在提供指令或数据值时，最初包含其最近访问的副本的高速缓存改变其指示以指示其副本现在被共享，并且访问该指令或数据值的处理单元此后被指示为具有高速缓存 最近访问的副本。 该协议允许由具有最近访问的副本的缓存直接（介入）在几个高速缓存之间共享的指令和数据值，而不从系统存储器（RAM）检索，显着地提高了计算机系统的处理速度。