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1.发明授权Method and apparatus for executing multiply-initiated, multiply-sourced variable delay system bus operations 失效用于执行多重启动的多来源可变延迟系统总线操作的方法和装置公开(公告)号：US06314495B1
公开(公告)日：2001-11-06
申请号：US09004144
申请日：1998-01-07
IPC分类号： G06F1200
CPC分类号： G06F9/524 , G06F12/0831
摘要： The present invention is a method and apparatus for preventing the occurrence of deadlocks from the execution of multiply-initiated multiply-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.
摘要翻译： 本发明是一种用于防止从多次发起的多来源可变延迟系统总线操作的执行中发生死锁的方法和装置。 一般来说，每个窥探者除了按照约定的条件同时给定操作。 换句话说，即使在重试操作时，给定缓存中的监听器也可以接受操作并开始处理。 此外，没有一个主动侦听器释放一个操作，直到所有的主动侦听器都完成了操作。 换句话说，给定操作的执行由窥探者同时开始，同时由每个窥探者完成。 这可以防止乒乓的死锁，因为任何一个缓存都不会在其他任何缓存之前完成操作。
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2.发明授权Method and apparatus for executing variable delay system bus operations of differing type or character without dead lock using shared buffers 失效用于使用共享缓冲器执行不同类型或字符的可变延迟系统总线操作而无死锁的方法和装置公开(公告)号：US06202131B1
公开(公告)日：2001-03-13
申请号：US09004147
申请日：1998-01-07
IPC分类号： G06F1300
CPC分类号： G06F12/0831
摘要： A method and apparatus for preventing the occurrence of deadlocks from the execution of variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. Execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others. The snoopers initiate operations at the same time based upon a common predefined event and ensure the operations end are finished concurrently when no outstanding retry operations are detected.
摘要翻译： 一种用于防止从可变延迟系统总线操作的执行中发生死锁的方法和装置。 一般来说，每个窥探者除了按照约定的条件同时给定操作。 换句话说，即使在重试操作时，给定缓存中的监听器也可以接受操作并开始处理。 此外，没有一个主动侦听器释放一个操作，直到所有的主动侦听器都完成了操作。 给定操作的执行由窥探者同时开始，同时由每个窥探者完成。 这可以防止乒乓的死锁，因为任何一个缓存都不会在其他任何缓存之前完成操作。 侦听器基于公共预定义事件同时启动操作，并确保在没有检测到未完成的重试操作时同时完成操作结束。
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3.发明授权公开(公告)号：US06192453B1
公开(公告)日：2001-02-20
申请号：US09114186
申请日：1998-07-13
IPC分类号： G06F1342
CPC分类号： G06F12/0831
摘要： A method and apparatus for preventing the occurrence of deadlocks from the execution of unresolvable system bus operations. In general, each snooper speculatively accepts a given operation when it has a snoop buffer available. However, rather than unconditionally processing the operation, the snooper waits to determine if another participant retried the operation due to unavailability of a snoop buffer. If some snooping participant retrys an operation, all snoopers that speculatively accepted an operation for processing abandon said operation. If no snooping participant retrys the operation, sufficient snooping resources were available for all necessary caches to begin processing the operation and the initiator can consider the operation completed. In other words, no operation is processed until all the necessary snooping resources are available to accept the operation. This prevents the system from getting into the ping-pong deadlock. Snoopers can safely assume that each presentation of an operation must be propagated and that no operation will have been fully or partially processed by some other snooper. The operation cannot proceed until all of the available resources are available and once available, the operation is propagated only once by those snooping resources.
摘要翻译： 一种用于防止从不可解决的系统总线操作的执行中发生死锁的方法和装置。 一般来说，每个窥探者在有一个snoop缓冲区可用时推测接受给定的操作。 然而，snooper不是无条件地处理这个操作，而是等待确定另一个参与者是否因侦听缓冲区不可用而重试操作。 如果一些侦听参与者重新开始一个操作，那么推测接受处理操作的所有窥探者都放弃了操作。 如果没有侦听参与者重新启动该操作，则可以使用足够的侦听资源进行所有必要的缓存，开始处理操作，启动器可以考虑完成该操作。 换句话说，在所有必需的窥探资源都可用于接受操作之前，不会处理任何操作。 这样可以防止系统进入乒乓僵死。 侦听器可以安全地假定每个演示的操作必须被传播，并且任何操作都不会被其他侦听器完全或部分地处理。 在所有可用资源可用并且一旦可用之前，该操作将无法继续，该操作仅被这些监听资源传播一次。
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4.发明授权Method and apparatus for executing self-snooped unresolvable system bus operations 失效执行自我侦测的无法解决的系统总线操作的方法和装置
公开(公告)号：US6141714A
公开(公告)日：2000-10-31
申请号：US114209
申请日：1998-07-13
CPC分类号： G06F9/524 , G06F12/0811 , G06F12/0831
摘要： A method and apparatus for preventing the occurrence of deadlocks from the execution of unresolvable system bus operations. In general, each snooper speculatively accepts a given operation when it has a snoop buffer available. However, rather than unconditionally processing the operation, the snooper waits to determine if another participant retried the operation due to unavailability of a snoop buffer. If some snooping participant retrys an operation, all snoopers that speculatively accepted an operation for processing abandon said operation. If no snooping participant retrys the operation, sufficient snooping resources were available for all necessary caches to begin processing the operation and the initiator can consider the operation completed. In other words, no operation is processed until all the necessary snooping resources are available to accept the operation. This prevents the system from getting into the ping-pong deadlock. Snoopers can safely assume that each presentation of an operation must be propagated and that no operation will have been fully or partially processed by some other snooper. The operation cannot proceed until all of the available resources are available and once available, the operation is propagated only once by those snooping resources.
摘要翻译： 一种用于防止从不可解决的系统总线操作的执行中发生死锁的方法和装置。 一般来说，每个窥探者在有一个snoop缓冲区可用时推测接受给定的操作。 然而，snooper不是无条件地处理这个操作，而是等待确定另一个参与者是否因侦听缓冲区不可用而重试操作。 如果一些侦听参与者重新开始一个操作，那么推测接受处理操作的所有窥探者都放弃了操作。 如果没有侦听参与者重新启动该操作，则可以使用足够的侦听资源进行所有必要的缓存，开始处理操作，启动器可以考虑完成该操作。 换句话说，在所有必需的窥探资源都可用于接受操作之前，不会处理任何操作。 这样可以防止系统进入乒乓僵死。 侦听器可以安全地假定每个演示的操作必须被传播，并且任何操作都不会被其他侦听器完全或部分地处理。 在所有可用资源可用并且一旦可用之前，该操作将无法继续，该操作仅被这些监听资源传播一次。
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5.发明授权Method and apparatus for executing multiply-initiated, multiply-sourced variable delay system bus operations 失效用于执行多重启动的多来源可变延迟系统总线操作的方法和装置
公开(公告)号：US6128705A
公开(公告)日：2000-10-03
申请号：US4148
申请日：1998-01-07
CPC分类号： G06F12/0831
摘要： A method and apparatus for preventing the occurrence of deadlocks from the execution of multiply-initiated multiply-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.
摘要翻译： 一种用于防止从多次发起的多来源可变延迟系统总线操作的执行中发生死锁的方法和装置。 一般来说，每个窥探者除了按照约定的条件同时给定操作。 换句话说，即使在重试操作时，给定缓存中的监听器也可以接受操作并开始处理。 此外，没有一个主动侦听器释放一个操作，直到所有的主动侦听器都完成了操作。 换句话说，给定操作的执行由窥探者同时开始，同时由每个窥探者完成。 这可以防止乒乓的死锁，因为任何一个缓存都不会在其他任何缓存之前完成操作。
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6.发明授权Method and apparatus for executing singly-initiated, singly-sourced variable delay system bus operations of differing character 失效用于单独启动的单源可变延迟系统总线操作的不同特性的方法和装置公开(公告)号：US06178485B1
公开(公告)日：2001-01-23
申请号：US09114187
申请日：1998-07-13
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： The present invention is a method and apparatus for preventing the occurrence of deadlocks from the execution of singly-initiated singly-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.
摘要翻译： 本发明是一种用于防止从单次发起的单源可变延迟系统总线操作的执行中发生死锁的方法和装置。 一般来说，每个窥探者除了按照约定的条件同时给定操作。 换句话说，即使在重试操作时，给定缓存中的监听器也可以接受操作并开始处理。 此外，没有一个主动侦听器释放一个操作，直到所有的主动侦听器都完成了操作。 换句话说，给定操作的执行由窥探者同时开始，同时由每个窥探者完成。 这可以防止乒乓的死锁，因为任何一个缓存都不会在其他任何缓存之前完成操作。
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7.发明授权Method and data processing system for microprocessor communication in a cluster-based multi-processor system 失效基于群集的多处理器系统中微处理器通信的方法和数据处理系统公开(公告)号：US07818364B2
公开(公告)日：2010-10-19
申请号：US11952479
申请日：2007-12-07
IPC分类号： G06F15/76 , G06F15/163
CPC分类号： H04L69/16 , G06F15/17 , H04L12/42 , H04L67/1002 , H04L69/161 , H04W28/14
摘要： A processor communication register (PCR) contained within a multiprocessor cluster system provides enhanced processor communication. The PCR stores information that is useful in pipelined or parallel multi-processing. Each processor cluster has exclusive rights to store to a sector within the PCR and has continuous access to read its contents. Each processor cluster updates its exclusive sector within the PCR, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译： 包含在多处理器集群系统内的处理器通信寄存器（PCR）提供增强的处理器通信。 PCR存储在流水线或并行多处理中有用的信息。 每个处理器集群具有存储到PCR中的扇区的独占权限，并且具有连续访问以读取其内容。 每个处理器集群在PCR中更新其独占部分，立即允许集群网络内的所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存行，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。
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8.发明授权Method, processing unit and data processing system for microprocessor communication in a multi-processor system 失效用于多处理器系统中微处理器通信的方法，处理单元和数据处理系统公开(公告)号：US07356568B2
公开(公告)日：2008-04-08
申请号：US10318514
申请日：2002-12-12
IPC分类号： G06F13/00
CPC分类号： G06F9/30101
摘要： A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
摘要翻译： 包含在多处理器系统内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。 每个处理器在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。 通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率 无限流的加载，存储和无效命令。
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公开(公告)号：US07017031B2
公开(公告)日：2006-03-21
申请号：US10268740
申请日：2002-10-10
IPC分类号： G06F9/30
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/0811
摘要： A data processing system includes a global promotion facility containing a plurality of promotion bit fields, an interconnect, and a plurality of processing units coupled to the global promotion facility and to the interconnect. A first processing unit includes an instruction sequencing unit, an execution unit that executes an acquisition instruction to acquire a particular promotion bit field within the global promotion facility, and a promotion awareness facility. In response to the first processing unit snooping a request by a second processing unit for the particular promotion bit field, the first processing unit records an association between the second processing unit and the particular promotion bit field in the global promotion facility. After the request and release of the particular promotion bit field by the first processing unit, the first processing unit checks the promotion awareness facility for an association for the particular promotion bit and responsive to the checking, pushes the particular promotion bit field to the second processing unit utilizing an unsolicited operation on the interconnect such that no additional request by the second processing unit is required.
摘要翻译： 数据处理系统包括包含多个升级位字段的全球推广设施，互连以及耦合到全球促销设施和互连的多个处理单元。 第一处理单元包括指令排序单元，执行单元，执行获取指令以获取全球促销设施内的特定促销位字段，以及促销意识设施。 响应于第一处理单元窥探特定促销位字段的第二处理单元的请求，第一处理单元在全局推广设备中记录第二处理单元和特定促销位字段之间的关联。 在由第一处理单元请求和释放特定促销位字段之后，第一处理单元检查促销感知设施以获得针对特定促销位的关联并且响应于检查，将特定促销位字段推送到第二处理 在所述互连上使用非请求操作的单元，使得不需要所述第二处理单元的附加请求。
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10.发明授权System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture 失效系统和方法能够使稳定的存储优势与稳定的存储架构相结合公开(公告)号：US06963967B1
公开(公告)日：2005-11-08
申请号：US09588508
申请日：2000-06-06
CPC分类号： G06F9/3851 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861
摘要： Disclosed is a method of processing instructions in a data processing system. An instruction sequence that includes a memory access instruction is received at a processor in program order. In response to receipt of the memory access instruction a memory access request and a barrier operation are created. The barrier operation is placed on an interconnect after the memory access request is issued to a memory system. After the barrier operation has completed, the memory access request is completed in program order. When the memory access request is a load request, the load request is speculatively issued if a barrier operation is pending. Data returned by the speculatively issued load request is only returned to a register or execution unit of the processor when an acknowledgment is received for the barrier operation.
摘要翻译： 公开了一种在数据处理系统中处理指令的方法。 包括存储器访问指令的指令序列以处理器的顺序被接收。 响应于接收到存储器访问指令，创建存储器访问请求和屏障操作。 在将存储器访问请求发布到存储器系统之后，屏障操作被放置在互连上。 屏障操作完成后，按程序顺序完成内存访问请求。 当存储器访问请求是加载请求时，如果屏障操作正在等待，则推测性地发出加载请求。 当接收到用于屏障操作的确认时，由推测发出的加载请求返回的数据仅返回到处理器的寄存器或执行单元。
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