公开(公告)号：US20090189141A1

公开(公告)日：2009-07-30

申请号：US12321670

申请日：2009-01-23

申请人： Jae-Min Shin ,  Jong-Woo Ko

发明人： Jae-Min Shin ,  Jong-Woo Ko

IPC分类号： H01L45/00

CPC分类号： H01L45/148 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16

摘要： A phase change memory device and a method of forming the same include a conductive pattern formed on a substrate. A lower electrode contact is disposed on the conductive pattern. The phase change pattern is disposed on the lower electrode contact. An upper electrode is disposed on the phase change pattern. An area of an upper surface of the lower electrode contact is smaller than an area of a lower surface of the lower electrode contact.

摘要翻译： 相变存储器件及其形成方法包括形成在衬底上的导电图案。 下电极接触件设置在导电图案上。 相变图案设置在下电极接触件上。 上电极设置在相变图案上。 下电极接触部的上表面的面积小于下电极接触面的下表面的面积。

公开(公告)号：US20090127538A1

公开(公告)日：2009-05-21

申请号：US12265262

申请日：2008-11-05

申请人： Kyung-Chang Ryoo ,  Jong-Woo Ko ,  Yoon-Jong Song

发明人： Kyung-Chang Ryoo ,  Jong-Woo Ko ,  Yoon-Jong Song

IPC分类号： H01L47/00

CPC分类号： H01L45/143 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675 ,  Y10S257/903

摘要： A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.

摘要翻译： 非易失性存储器阵列包括相变存储元件的阵列，它们通过在可相变存储元件阵列之间延伸的至少第一电绝缘区域彼此电绝缘。 第一电绝缘区域中包括多个空隙。 这些空隙中的每一个在非易失性存储器阵列中相应的一对相位可变存储单元之间延伸，并且总体上空隙在第一电绝缘区域中形成一组空隙。

公开(公告)号：US20080073759A1

公开(公告)日：2008-03-27

申请号：US11555182

申请日：2006-10-31

申请人： Sun-Pil Youn ,  Jong-Woo Ko ,  Jeong-Jin Lee

发明人： Sun-Pil Youn ,  Jong-Woo Ko ,  Jeong-Jin Lee

IPC分类号： H01L23/495

CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/01049

摘要： Provided is a semiconductor package including a high integration semiconductor chip and having a minimum area to be mounted on a circuit board. The semiconductor package includes a semiconductor chip, a plurality of inner leads, and an encapsulant. The plurality of inner leads include upper and bottom surfaces and are electrically connected to the semiconductor chip. The encapsulant covers the semiconductor chip and the plurality of inner leads. The upper surfaces of the plurality of inner leads are fixed to the encapsulant, portions of the bottom surfaces of the plurality of inner leads are exposed from the encapsulant, and the bottom surfaces of the plurality of inner leads are disposed at a different height from a bottom surface of the encapsulant.

摘要翻译： 提供了包括高集成度半导体芯片并且具有要安装在电路板上的最小面积的半导体封装。 半导体封装包括半导体芯片，多个内部引线和密封剂。 多个内引线包括上表面和下表面，并且电连接到半导体芯片。 密封剂覆盖半导体芯片和多个内部引线。 多个内部引线的上表面固定在密封剂上，多个内部引线的底面的一部分从密封剂露出，多个内部引线的底面设置在与 密封剂的底面。

公开(公告)号：US07777214B2

公开(公告)日：2010-08-17

申请号：US12321670

申请日：2009-01-23

申请人： Jae-Min Shin ,  Jong-Woo Ko

发明人： Jae-Min Shin ,  Jong-Woo Ko

IPC分类号： H01L29/02

CPC分类号： H01L45/148 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/16

摘要： A phase change memory device and a method of forming the same include a conductive pattern formed on a substrate. A lower electrode contact is disposed on the conductive pattern. The phase change pattern is disposed on the lower electrode contact. An upper electrode is disposed on the phase change pattern. An area of an upper surface of the lower electrode contact is smaller than an area of a lower surface of the lower electrode contact.

摘要翻译： 相变存储器件及其形成方法包括形成在衬底上的导电图案。 下电极接触件设置在导电图案上。 相变图案设置在下电极接触件上。 上电极设置在相变图案上。 下电极接触部的上表面的面积小于下电极接触面的下表面的面积。

公开(公告)号：US07977662B2

公开(公告)日：2011-07-12

申请号：US12265262

申请日：2008-11-05

申请人： Kyung-Chang Ryoo ,  Jong-Woo Ko ,  Yoon-Jong Song

发明人： Kyung-Chang Ryoo ,  Jong-Woo Ko ,  Yoon-Jong Song

IPC分类号： H01L29/06 ,  H01L47/00

CPC分类号： H01L45/143 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675 ,  Y10S257/903

摘要： A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.

摘要翻译： 非易失性存储器阵列包括相变存储元件的阵列，它们通过在可相变存储元件阵列之间延伸的至少第一电绝缘区域彼此电绝缘。 第一电绝缘区域中包括多个空隙。 这些空隙中的每一个在非易失性存储器阵列中相应的一对相位可变存储单元之间延伸，并且总体上空隙在第一电绝缘区域中形成一组空隙。

公开(公告)号：US20080073772A1

公开(公告)日：2008-03-27

申请号：US11555155

申请日：2006-10-31

申请人： Sun-Pil YOUN ,  Jong-Woo KO ,  Jeong-Jin LEE

发明人： Sun-Pil YOUN ,  Jong-Woo KO ,  Jeong-Jin LEE

IPC分类号： H01L23/48

CPC分类号： H01L23/49551 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/01049

摘要： Provided are highly reliable, high density stacked semiconductor packages including a plurality of semiconductor chips and a method of manufacturing the highly reliable, high density semiconductor package. An embodiment of the stacked semiconductor package includes upper and lower semiconductor packages that are sequentially stacked. The upper and lower semiconductor packages include inner leads connected to semiconductor chips. The lower semiconductor package may further include a plurality of outer leads connected to the inner leads of the lower semiconductor package and that extend outside a encapsulant to be electrically connected to the inner leads of the upper semiconductor package.

摘要翻译： 提供了包括多个半导体芯片的高可靠性，高密度堆叠半导体封装以及制造高可靠性，高密度半导体封装的方法。 叠层半导体封装的一个实施例包括依次层叠的上下半导体封装。 上半导体封装和下半导体封装包括连接到半导体芯片的内部引线。 下部半导体封装还可以包括连接到下部半导体封装的内部引线的多个外部引线，并且延伸到密封剂外部以电连接到上部半导体封装的内部引线。

公开(公告)号：US07629677B2

公开(公告)日：2009-12-08

申请号：US11555182

申请日：2006-10-31

申请人： Sun-Pil Youn ,  Jong-Woo Ko ,  Jeong-Jin Lee

发明人： Sun-Pil Youn ,  Jong-Woo Ko ,  Jeong-Jin Lee

IPC分类号： H01L23/495 ,  H01R9/00 ,  H01L21/00

CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/01049

摘要： Provided is a semiconductor package including a high integration semiconductor chip and having a minimum area to be mounted on a circuit board. The semiconductor package includes a semiconductor chip, a plurality of inner leads, and an encapsulant. The plurality of inner leads include upper and bottom surfaces and are electrically connected to the semiconductor chip. The encapsulant covers the semiconductor chip and the plurality of inner leads. The upper surfaces of the plurality of inner leads are fixed to the encapsulant, portions of the bottom surfaces of the plurality of inner leads are exposed from the encapsulant, and the bottom surfaces of the plurality of inner leads are disposed at a different height from a bottom surface of the encapsulant.

摘要翻译： 提供了包括高集成度半导体芯片并且具有要安装在电路板上的最小面积的半导体封装。 半导体封装包括半导体芯片，多个内部引线和密封剂。 多个内引线包括上表面和下表面，并且电连接到半导体芯片。 密封剂覆盖半导体芯片和多个内部引线。 多个内部引线的上表面固定在密封剂上，多个内部引线的底面的一部分从密封剂露出，多个内部引线的底面设置在与 密封剂的底面。