公开(公告)号：US07888768B2

公开(公告)日：2011-02-15

申请号：US11329268

申请日：2006-01-09

申请人： Sung-lyong Kim ,  Chang-ki Jeon ,  Jong-jib Kim ,  Jong-tae Hwang

发明人： Sung-lyong Kim ,  Chang-ki Jeon ,  Jong-jib Kim ,  Jong-tae Hwang

IPC分类号： H01L21/70 ,  H01L21/77

CPC分类号： H01L29/808 ,  H01L27/088

摘要： In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device. The high-side power switch is turned on when a predetermined voltage is applied to the source of the low voltage transistor, a voltage higher than the predetermined voltage is applied to the drain of the high voltage transistor, and a voltage level of the control signal becomes higher than the predetermined voltage by a threshold voltage of the low voltage transistor.

摘要翻译： 在一个实施例中，提供了功率集成电路器件。 功率集成电路装置包括具有高压晶体管和低压晶体管的高侧电源开关。 高压晶体管具有栅极，源极和漏极，并且能够承受施加到其漏极的高电压。 低压晶体管具有栅极，源极和漏极，其中低压晶体管的漏极连接到高压晶体管的源极，并且低压晶体管的源极连接到高电压的栅极 晶体管，并且其中控制信号从功率集成电路器件施加到低电压晶体管的栅极。 当向低电压晶体管的源极施加预定电压时，高侧电源开关接通，将高于预定电压的电压施加到高电压晶体管的漏极，并且控制信号的电压电平 通过低压晶体管的阈值电压变得高于预定电压。

公开(公告)号：US20070158681A1

公开(公告)日：2007-07-12

申请号：US11329268

申请日：2006-01-09

申请人： Sung-lyong Kim ,  Chang-ki Jeon ,  Jong-jib Kim ,  Jong-tae Hwang

发明人： Sung-lyong Kim ,  Chang-ki Jeon ,  Jong-jib Kim ,  Jong-tae Hwang

IPC分类号： H01L29/74

CPC分类号： H01L29/808 ,  H01L27/088

摘要： In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device. The high-side power switch is turned on when a predetermined voltage is applied to the source of the low voltage transistor, a voltage higher than the predetermined voltage is applied to the drain of the high voltage transistor, and a voltage level of the control signal becomes higher than the predetermined voltage by a threshold voltage of the low voltage transistor.

摘要翻译： 在一个实施例中，提供了功率集成电路器件。 功率集成电路装置包括具有高压晶体管和低压晶体管的高侧电源开关。 高压晶体管具有栅极，源极和漏极，并且能够承受施加到其漏极的高电压。 低压晶体管具有栅极，源极和漏极，其中低压晶体管的漏极连接到高压晶体管的源极，并且低压晶体管的源极连接到高电压的栅极 晶体管，并且其中控制信号从功率集成电路器件施加到低电压晶体管的栅极。 当向低电压晶体管的源极施加预定电压时，高侧电源开关接通，将高于预定电压的电压施加到高压晶体管的漏极，并且控制信号的电压电平 通过低压晶体管的阈值电压变得高于预定电压。

公开(公告)号：US06600206B2

公开(公告)日：2003-07-29

申请号：US10123007

申请日：2002-04-15

申请人： Chang-ki Jeon ,  Sung-Iyong Kim ,  Jong-jib Kim

发明人： Chang-ki Jeon ,  Sung-Iyong Kim ,  Jong-jib Kim

IPC分类号： H01L2900

CPC分类号： H01L29/7816 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095

摘要： A high voltage semiconductor device is provided. The high voltage semiconductor device includes a tow voltage region, a high voltage region, and a high breakdown voltage isolation region. The high voltage region is surrounded by the low voltage region and has corner portions at one side thereof. The high breakdown voltage isolation region has an isolation region for electrically separating the low and high voltage regions from each other and a lateral double diffused metal-oxide-semiconductor (DMOS) transistor for transmitting a signal from the low voltage region to the high voltage region. In particular, a drain region of the lateral DMOS transistor is disposed between the corner portions of the high voltage region, and opposite edges of the corner portions of the high voltage region and drain region of the lateral DMOS transistor are curved.

摘要翻译： 提供高压半导体器件。 高电压半导体器件包括丝束电压区域，高电压区域和高击穿电压隔离区域。 高电压区域被低电压区域包围，并且在其一侧具有角部。 高击穿电压隔离区域具有用于将低电压区域和高电压区域彼此电隔离的隔离区域和用于将信号从低电压区域传输到高电压区域的横向双扩散金属氧化物半导体（DMOS）晶体管 。 特别地，横向DMOS晶体管的漏极区域设置在高电压区域的角部之间，并且横向DMOS晶体管的高压区域和漏极区域的拐角部分的相对边缘是弯曲的。

公开(公告)号：US06486512B2

公开(公告)日：2002-11-26

申请号：US09790815

申请日：2001-02-23

申请人： Chang-ki Jeon ,  Jong-jib Kim ,  Young-suk Choi ,  Chang-seong Choi ,  Min-whan Kim

发明人： Chang-ki Jeon ,  Jong-jib Kim ,  Young-suk Choi ,  Chang-seong Choi ,  Min-whan Kim

IPC分类号： H01L2976

CPC分类号： H01L29/0692 ,  H01L29/0696 ,  H01L29/7835

摘要： A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined region of right and left and upper portions of the projected portion. Two drain structures are formed in a predetermined region surrounded by the source structure. Extended drain structures are formed around the drain structures and the extended drain structures function as a channel with a field effect channel between sides of the projected portion of the source structure. Accordingly, since there are no drain structures on the tip of the projected portion of the source structure, although a radius of curvature of the tip of the projected portion is small, a decrease in a breakdown voltage of a device due to the small radius of curvature of the tip of the projected portion can be suppressed. As a result, a power semiconductor device having a small radius of curvature of the source structure and a high breakdown voltage can be provided.

摘要翻译： 提供了功率半导体器件及其制造方法。 功率半导体器件包括源结构，其具有在其中心具有尖端形状的端部的突出部分并且形成为围绕突出部分的左右上部的预定区域。 在由源结构包围的预定区域中形成两个漏极结构。 在漏极结构周围形成扩展的漏极结构，并且延伸的漏极结构用作具有源结构的突出部分的侧面之间的场效应沟道的沟道。 因此，由于在源极结构的突出部分的尖端上没有漏极结构，尽管突出部分的尖端的曲率半径小，但是由于半径小的部件，器件的击穿电压降低 可以抑制突出部分的尖端的弯曲。 结果，可以提供具有较小的源结构曲率半径和高击穿电压的功率半导体器件。

公开(公告)号：US06995453B2

公开(公告)日：2006-02-07

申请号：US10241818

申请日：2002-09-10

申请人： Jong-jib Kim ,  Chang-ki Jeon ,  Sung-lyong Kim ,  Young-suk Choi ,  Min-hwan Kim

发明人： Jong-jib Kim ,  Chang-ki Jeon ,  Sung-lyong Kim ,  Young-suk Choi ,  Min-hwan Kim

IPC分类号： H01L27/102 ,  H01L29/70

CPC分类号： H01L21/761 ,  H01L27/0623 ,  H01L29/7322

摘要： In a high voltage integrated circuit, a low voltage region is separated from a high voltage region by a junction termination. A bipolar transistor in the high voltage region is surrounded by an isolation region having a low doping concentration. The use of a low-doped isolation region increases the size of an active region without reduction of a breakdown voltage.

公开(公告)号：US06909143B2

公开(公告)日：2005-06-21

申请号：US10818330

申请日：2004-04-02

申请人： Chang-Ki Jeon ,  Jong-Jib Kim ,  Young-Suk Choi

发明人： Chang-Ki Jeon ,  Jong-Jib Kim ,  Young-Suk Choi

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L31/113

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7809

摘要： A lateral double-diffused MOS (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate 202 formed of a material having p-conductivity type impurities, a drift region formed of a material having n-conductivity type impurities on the semiconductor substrate, a first buried layer 206 of p-type material and a second buried layer 208 formed of n-type material. Layers 206 and 208 are arranged at the boundary between the semiconductor substrate and the drift region. A first well region 210 of p-type material contacts the first buried layer 206 n-type in a first portion 1 of the drift region. A first source region 214 conductivity in a predetermined upper region of the first well region, a drain region formed of a material having second conductivity type impurities in a predetermined region of the drift region, the drain region being spaced a predetermined gap apart from the first well region, a third buried layer formed of a material having first conductivity type impurities in a second region of the drift region, the third buried layer being overlapped with a part of an upper portion of the first buried layer, a second well region formed of a material having first conductivity type impurities in the second region of the drift region, the second well region being overlapped with the third buried layer, a second source region formed of a material having second conductivity type impurities in a predetermined upper region of the second well region, a gate insulating layer formed in a first channel region inside the first well region and in a second channel region inside the second well region, a gate electrode formed on the gate insulating layer, a source electrode formed to be electrically connected to the first source region and the second source region, and a drain electrode formed to be electrically connected to the drain region.