公开(公告)号：US06486512B2

公开(公告)日：2002-11-26

申请号：US09790815

申请日：2001-02-23

申请人： Chang-ki Jeon ,  Jong-jib Kim ,  Young-suk Choi ,  Chang-seong Choi ,  Min-whan Kim

发明人： Chang-ki Jeon ,  Jong-jib Kim ,  Young-suk Choi ,  Chang-seong Choi ,  Min-whan Kim

IPC分类号： H01L2976

CPC分类号： H01L29/0692 ,  H01L29/0696 ,  H01L29/7835

摘要： A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined region of right and left and upper portions of the projected portion. Two drain structures are formed in a predetermined region surrounded by the source structure. Extended drain structures are formed around the drain structures and the extended drain structures function as a channel with a field effect channel between sides of the projected portion of the source structure. Accordingly, since there are no drain structures on the tip of the projected portion of the source structure, although a radius of curvature of the tip of the projected portion is small, a decrease in a breakdown voltage of a device due to the small radius of curvature of the tip of the projected portion can be suppressed. As a result, a power semiconductor device having a small radius of curvature of the source structure and a high breakdown voltage can be provided.

摘要翻译： 提供了功率半导体器件及其制造方法。 功率半导体器件包括源结构，其具有在其中心具有尖端形状的端部的突出部分并且形成为围绕突出部分的左右上部的预定区域。 在由源结构包围的预定区域中形成两个漏极结构。 在漏极结构周围形成扩展的漏极结构，并且延伸的漏极结构用作具有源结构的突出部分的侧面之间的场效应沟道的沟道。 因此，由于在源极结构的突出部分的尖端上没有漏极结构，尽管突出部分的尖端的曲率半径小，但是由于半径小的部件，器件的击穿电压降低 可以抑制突出部分的尖端的弯曲。 结果，可以提供具有较小的源结构曲率半径和高击穿电压的功率半导体器件。

公开(公告)号：US06995453B2

公开(公告)日：2006-02-07

申请号：US10241818

申请日：2002-09-10

申请人： Jong-jib Kim ,  Chang-ki Jeon ,  Sung-lyong Kim ,  Young-suk Choi ,  Min-hwan Kim

发明人： Jong-jib Kim ,  Chang-ki Jeon ,  Sung-lyong Kim ,  Young-suk Choi ,  Min-hwan Kim

IPC分类号： H01L27/102 ,  H01L29/70

CPC分类号： H01L21/761 ,  H01L27/0623 ,  H01L29/7322

摘要： In a high voltage integrated circuit, a low voltage region is separated from a high voltage region by a junction termination. A bipolar transistor in the high voltage region is surrounded by an isolation region having a low doping concentration. The use of a low-doped isolation region increases the size of an active region without reduction of a breakdown voltage.

公开(公告)号：US06833585B2

公开(公告)日：2004-12-21

申请号：US10120207

申请日：2002-04-10

申请人： Min-hwan Kim ,  Chang-ki Jeon ,  Young-suk Choi

发明人： Min-hwan Kim ,  Chang-ki Jeon ,  Young-suk Choi

IPC分类号： H01L2976

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/7835

摘要： A high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor includes a plurality of well regions of a first conductivity type formed to be spaced out within a well region of a second conductivity type between a channel region of the first conductivity type and a drain region of the second conductivity type. Most current is carried through some portions of the well region of the second conductivity type in which the well regions of the first conductivity do not appear so that the current carrying performance of the device is improved. When a bias voltage is applied to the drain region, the well region of the second conductivity type is completely depleted at other portions where the well region of the second conductivity type and the well regions of the first conductivity type alternately appear so that the breakdown voltage of the device can be increased. In addition, since the well region of the second conductivity type can be easily depleted, not only the breakdown voltage can be increased, but also the impurity concentration of the well region of the second conductivity type can be increased. Accordingly, the on-resistance of the device can be decreased.

摘要翻译： 高压横向双扩散金属氧化物半导体（DMOS）晶体管包括多个第一导电类型的阱区，其形成为在第一导电类型的沟道区域和漏极之间的第二导电类型的阱区域内间隔开 第二导电类型的区域。 大多数电流通过第二导电类型的阱区的一些部分被携带，其中第一导电性的阱区不出现，从而提高了器件的载流性能。 当偏置电压施加到漏极区域时，第二导电类型的阱区域在第二导电类型的阱区域和第一导电类型的阱区域交替出现的其它部分完全耗尽，使得击穿电压 的设备可以增加。 此外，由于第二导电类型的阱区域容易耗尽，不仅可以提高击穿电压，而且能够提高第二导电型阱区的杂质浓度。 因此，可以降低器件的导通电阻。

公开(公告)号：US20130236639A1

公开(公告)日：2013-09-12

申请号：US13415808

申请日：2012-03-08

申请人： Matthew J. Carey ,  Shekar B. Chandrashekariaih ,  Jeffrey R. Childress ,  Young-suk Choi ,  John Creighton Read

发明人： Matthew J. Carey ,  Shekar B. Chandrashekariaih ,  Jeffrey R. Childress ,  Young-suk Choi ,  John Creighton Read

IPC分类号： G11B5/127

CPC分类号： G11B5/3163 ,  G01R33/093 ,  G11B5/3906 ,  H01F10/1936 ,  H01F10/3268 ,  H01F10/3295 ,  H01F41/303 ,  H01L43/08 ,  H01L43/12

摘要： A method for making a current-perpendicular-to the-plane giant magnetoresistance (CPP-GMR) sensor with a Heusler alloy pinned layer on the sensor's Mn-containing antiferromagnetic pinning layer uses two annealing steps. A layer of a crystalline non-Heusler alloy ferromagnetic material, like Co or CoFe, is deposited on the antiferromagnetic pinning layer and a layer of an amorphous X-containing ferromagnetic alloy, like a CoFeBTa layer, is deposited on the Co or CoFe crystalline layer. After a first in-situ annealing of the amorphous X-containing ferromagnetic alloy, the Heusler alloy pinned layer is deposited on the amorphous X-containing ferromagnetic layer and a second high-temperature annealing step is performed to improve the microstructure of the Heusler alloy pinned layer.

摘要翻译： 在传感器的含Mn反铁磁性钉扎层上制造具有Heusler合金钉扎层的电流垂直于平面的巨磁电阻（CPP-GMR）传感器的方法采用两个退火步骤。 一层结晶的非Heusler合金铁磁材料，如Co或CoFe，沉积在反铁磁性钉扎层上，并且含有非晶态的含铁铁磁性合金如CoFeBTa层沉积在Co或CoFe晶体层上 。 在非晶态含铁铁磁性合金的第一次原位退火之后，将Heusler合金钉扎层沉积在含非晶态的铁磁性层上，并执行第二个高温退火步骤，以改善Heusler合金被钉扎的微结构 层。

公开(公告)号：US08617644B2

公开(公告)日：2013-12-31

申请号：US13415808

申请日：2012-03-08

申请人： Matthew J. Carey ,  Shekar B Chandrashekariaih ,  Jeffrey R. Childress ,  Young-suk Choi ,  John Creighton Read

发明人： Matthew J. Carey ,  Shekar B Chandrashekariaih ,  Jeffrey R. Childress ,  Young-suk Choi ,  John Creighton Read

IPC分类号： G11B5/84

CPC分类号： G11B5/3163 ,  G01R33/093 ,  G11B5/3906 ,  H01F10/1936 ,  H01F10/3268 ,  H01F10/3295 ,  H01F41/303 ,  H01L43/08 ,  H01L43/12

摘要： A method for making a current-perpendicular-to the-plane giant magnetoresistance (CPP-GMR) sensor with a Heusler alloy pinned layer on the sensor's Mn-containing antiferromagnetic pinning layer uses two annealing steps. A layer of a crystalline non-Heusler alloy ferromagnetic material, like Co or CoFe, is deposited on the antiferromagnetic pinning layer and a layer of an amorphous X-containing ferromagnetic alloy, like a CoFeBTa layer, is deposited on the Co or CoFe crystalline layer. After a first in-situ annealing of the amorphous X-containing ferromagnetic alloy, the Heusler alloy pinned layer is deposited on the amorphous X-containing ferromagnetic layer and a second high-temperature annealing step is performed to improve the microstructure of the Heusler alloy pinned layer.

摘要翻译： 在传感器的含Mn反铁磁性钉扎层上制造具有Heusler合金钉扎层的电流垂直于平面的巨磁电阻（CPP-GMR）传感器的方法采用两个退火步骤。 一层结晶的非Heusler合金铁磁材料，如Co或CoFe，沉积在反铁磁性钉扎层上，并且含有非晶态的含铁铁磁性合金如CoFeBTa层沉积在Co或CoFe晶体层上 。 在非晶态含铁铁磁性合金的第一次原位退火之后，将Heusler合金钉扎层沉积在含非晶态的铁磁性层上，并执行第二个高温退火步骤，以改善Heusler合金被钉扎的微结构 层。

公开(公告)号：US08278123B2

公开(公告)日：2012-10-02

申请号：US13037796

申请日：2011-03-01

申请人： Young-suk Choi ,  Yuichi Otani

发明人： Young-suk Choi ,  Yuichi Otani

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G01R33/098 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3277 ,  H01F41/307

摘要： MgO-based magnetic tunnel junction (MTJ) device includes in essence a ferromagnetic reference layer, a MgO tunnel barrier and a ferromagnetic free layer. The microstructure of MgO tunnel barrier, which is prepared by the metallic Mg deposition followed by the oxidation process or reactive sputtering, is amorphous or microcrystalline with poor (001) out-of-plane texture. In the present invention at least only the ferromagnetic reference layer or both of the ferromagnetic reference and free layer is proposed to be bi-layer structure having a crystalline preferred grain growth promotion (PGGP) seed layer adjacent to the tunnel barrier. This crystalline PGGP seed layer induces the crystallization and the preferred grain growth of the MgO tunnel barrier upon post-deposition annealing.

摘要翻译： 基于MgO的磁隧道结（MTJ）装置本质上包括铁磁参考层，MgO隧道势垒和铁磁自由层。 通过金属Mg沉积随后进行氧化处理或反应溅射制备的MgO隧道势垒的微结构是无定形或微晶的，具有差（001）面外结构。 在本发明中，至少只有铁磁参考层或铁磁参考层和自由层两者被提议为具有与隧道势垒相邻的晶体优选晶粒生长促进（PGGP）种子层的双层结构。 该结晶PGGP晶种层在后沉积退火时诱导MgO隧道势垒的结晶和优选的晶粒生长。

公开(公告)号：US08143611B2

公开(公告)日：2012-03-27

申请号：US12872497

申请日：2010-08-31

申请人： Young-suk Choi ,  Koji Tsunekawa

发明人： Young-suk Choi ,  Koji Tsunekawa

IPC分类号： H01L45/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675 ,  H01L45/1683 ,  Y10S438/90

摘要： A phase-change memory element includes a perovskite layer formed by a material having a perovskite structure, and a phase-change recording material layer which is formed on the perovskite layer, and changes the phase to a crystal state or amorphous state when supplied with an electric current via the perovskite layer.

摘要翻译： 相变存储元件包括由具有钙钛矿结构的材料形成的钙钛矿层和形成在钙钛矿层上的相变记录材料层，并且当被供给时，将相位改变为晶体状态或非晶态 通过钙钛矿层的电流。

公开(公告)号：US08611053B2

公开(公告)日：2013-12-17

申请号：US13415813

申请日：2012-03-08

申请人： Elizabeth Ann Brinkman ,  Matthew J. Carey ,  Jeffrey R. Childress ,  Young-suk Choi ,  Brian R. York

发明人： Elizabeth Ann Brinkman ,  Matthew J. Carey ,  Jeffrey R. Childress ,  Young-suk Choi ,  Brian R. York

IPC分类号： G11B5/39

CPC分类号： G11B5/3906 ,  H01F10/1936 ,  H01F10/325 ,  H01F10/3272 ,  H01F10/3295 ,  H01L43/08 ,  H01L43/10

摘要： A current-perpendicular-to-the-plane giant magnetoresistance (CPP-GMR) sensor has a multilayer reference layer containing a Heusler alloy. The multilayer reference layer may be a simple pinned layer or the AP2 layer of an antiparallel (AP)-pinned structure. The multilayer reference layer is formed of a crystalline non-Heusler alloy ferromagnetic layer on either an antiferromagnetic layer (in a simple pinned structure) or an antiparallel coupling (APC) layer (in an AP-pinned structure), a Heusler alloy layer adjacent the sensor's nonmagnetic electrically conducting spacer layer, and an intermediate substantially non-crystalline X-containing layer between the crystalline non-Heusler alloy layer and the Heusler alloy layer. The element X is selected from one or more of tantalum (Ta), hafnium (Hf), niobium (Nb) and boron (B).

摘要翻译： 电流垂直于平面的巨磁电阻（CPP-GMR）传感器具有包含Heusler合金的多层参考层。 多层参考层可以是简单的钉扎层或反平行（AP）钉结构的AP2层。 多层参考层由反铁磁层（简单的钉扎结构）或反平行耦合（APC）层（AP钉扎结构）中的结晶非Heusler合金铁磁层形成，与之相邻的Heusler合金层 传感器的非磁性导电间隔层，以及在结晶非Heusler合金层和Heusler合金层之间的中间基本上非结晶的含X的层。 元素X选自钽（Ta），铪（Hf），铌（Nb）和硼（B）中的一种或多种。

公开(公告)号：US20130236744A1

公开(公告)日：2013-09-12

申请号：US13415813

申请日：2012-03-08

申请人： Elizabeth Ann Brinkman ,  Matthew J. Carey ,  Jeffrey R. Childress ,  Young-suk Choi ,  Brian R. York

发明人： Elizabeth Ann Brinkman ,  Matthew J. Carey ,  Jeffrey R. Childress ,  Young-suk Choi ,  Brian R. York

IPC分类号： G11B5/39

CPC分类号： G11B5/3906 ,  H01F10/1936 ,  H01F10/325 ,  H01F10/3272 ,  H01F10/3295 ,  H01L43/08 ,  H01L43/10

摘要： A current-perpendicular-to-the-plane giant magnetoresistance (CPP-GMR) sensor has a multilayer reference layer containing a Heusler alloy. The multilayer reference layer may be a simple pinned layer or the AP2 layer of an antiparallel (AP)-pinned structure. The multilayer reference layer is formed of a crystalline non-Heusler alloy ferromagnetic layer on either an antiferromagnetic layer (in a simple pinned structure) or an antiparallel coupling (APC) layer (in an AP-pinned structure), a Heusler alloy layer adjacent the sensor's nonmagnetic electrically conducting spacer layer, and an intermediate substantially non-crystalline X-containing layer between the crystalline non-Heusler alloy layer and the Heusler alloy layer. The element X is selected from one or more of tantalum (Ta), hafnium (Hf), niobium (Nb) and boron (B).

摘要翻译： 电流垂直于平面的巨磁电阻（CPP-GMR）传感器具有包含Heusler合金的多层参考层。 多层参考层可以是简单的钉扎层或反平行（AP）钉结构的AP2层。 多层参考层由反铁磁层（简单的钉扎结构）或反平行耦合（APC）层（AP钉扎结构）中的结晶非Heusler合金铁磁层形成，与之相邻的Heusler合金层 传感器的非磁性导电间隔层，以及在结晶非Heusler合金层和Heusler合金层之间的中间基本上非结晶的含X的层。 元素X选自钽（Ta），铪（Hf），铌（Nb）和硼（B）中的一种或多种。

公开(公告)号：US08318510B2

公开(公告)日：2012-11-27

申请号：US12872374

申请日：2010-08-31

申请人： Young-suk Choi

发明人： Young-suk Choi

IPC分类号： H01L43/12

CPC分类号： H01F10/3254 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F41/307 ,  H01L43/12 ,  Y10T29/5313

摘要： A method of manufacturing a magnetoresistive element includes a tunnel barrier forming step. The tunnel barrier forming step comprises a metal layer forming step of forming a metal layer to have a first thickness, a plasma processing step of performing a plasma treatment which exposes the metal layer to a plasma of an inert gas to etch the metal layer to have a second thickness smaller than the first thickness, and an oxidation step of oxidizing the metal layer having undergone the plasma treatment to form a metal oxide which forms a tunnel barrier.

摘要翻译： 磁阻元件的制造方法包括隧道势垒形成工序。 隧道势垒形成步骤包括形成具有第一厚度的金属层的金属层形成步骤，执行等离子体处理的等离子体处理步骤，其将金属层暴露于惰性气体的等离子体以蚀刻金属层以具有 小于第一厚度的第二厚度，以及氧化已经经历等离子体处理的金属层以形成形成隧道势垒的金属氧化物的氧化步骤。