公开(公告)号：US08402419B1

公开(公告)日：2013-03-19

申请号：US13009467

申请日：2011-01-19

申请人： Jordan Plofsky ,  Philippe Molson ,  Francois Pequillat

发明人： Jordan Plofsky ,  Philippe Molson ,  Francois Pequillat

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Power consumption estimation is performed at the system level in a design process, thus allowing early evaluation of feasibility and other considerations relating to logic/DSP design and hardware implementation of a proposed electronic design. Evaluation of the system level power consumption estimate(s) permits adjustment of a system level representation of the proposed electronic design, prior to investment of substantial resources in the electronic design. Other estimates, including other power consumption estimates, may be performed to adjust the proposed electronic design as well. Such estimates may be made in response to gate level power consumption estimates and/or hardware level power consumption estimates.

摘要翻译： 功耗估计在设计过程中在系统级进行，从而允许对提出的电子设计的逻辑/ DSP设计和硬件实现的可行性和其他考虑的早期评估。 在电子设计中投入大量资源之前，系统级功耗估计的评估允许调整所提出的电子设计的系统级表示。 可以执行其他估计，包括其他功耗估计，以调整拟议的电子设计。 这样的估计可以响应于门级功耗估计和/或硬件级功耗估计而进行。

公开(公告)号：US08758961B1

公开(公告)日：2014-06-24

申请号：US13246761

申请日：2011-09-27

申请人： Jordan Plofsky ,  Chooi Pei Lim ,  Danny Biran ,  Francis Man-Chit Chow

发明人： Jordan Plofsky ,  Chooi Pei Lim ,  Danny Biran ,  Francis Man-Chit Chow

IPC分类号： G03F9/00

CPC分类号： H01L21/283 ,  G03F1/00 ,  G03F1/50 ,  H01L21/78 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

摘要： A mask set is described. In one implementation, the mask set includes: a first layer mask including a plurality of first tiles of a first tile size; and a second layer mask including a plurality of second tiles of a second tile size, where the second tile size is different from the first tile size. Also, a method of fabricating a plurality of integrated circuits (ICs) is described. In one implementation, the method includes: using a first layer mask having a first tile size to fabricate a first layer of a first IC of the plurality of ICs and a first layer of a second IC of the plurality of ICs; and using a second layer mask having a second tile size to fabricate a second layer of the first IC, where the second tile size is different from the first tile size.

摘要翻译： 描述掩模集。 在一个实现中，掩模集包括：第一层掩模，其包括具有第一块尺寸的多个第一瓦片; 以及第二层掩模，其包括第二块尺寸的多个第二块，其中第二块尺寸不同于第一块尺寸。 此外，描述了制造多个集成电路（IC）的方法。 在一个实现中，该方法包括：使用具有第一块尺寸的第一层掩模来制造多个IC中的第一IC的第一层和多个IC中的第二IC的第一层; 以及使用具有第二块尺寸的第二层掩模来制造所述第一IC的第二层，其中所述第二块尺寸不同于所述第一块尺寸。

公开(公告)号：US07882457B1

公开(公告)日：2011-02-01

申请号：US11600436

申请日：2006-11-15

申请人： Jordan Plofsky ,  Philippe Molson ,  Francois Pequillat

发明人： Jordan Plofsky ,  Philippe Molson ,  Francois Pequillat

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Power consumption estimation is performed at the system level in a design process, thus allowing early evaluation of feasibility and other considerations relating to logic/DSP design and hardware implementation of a proposed electronic design. Evaluation of the system level power consumption estimate(s) permits adjustment of a system level representation of the proposed electronic design, prior to investment of substantial resources in the electronic design. Other estimates, including other power consumption estimates, may be performed to adjust the proposed electronic design as well. Such estimates may be made in response to gate level power consumption estimates and/or hardware level power consumption estimates.

摘要翻译： 功耗估计在设计过程中在系统级进行，从而允许对提出的电子设计的逻辑/ DSP设计和硬件实现的可行性和其他考虑的早期评估。 在电子设计中投入大量资源之前，系统级功耗估计的评估允许调整所提出的电子设计的系统级表示。 可以执行其他估计，包括其他功耗估计，以调整拟议的电子设计。 这样的估计可以响应于门级功耗估计和/或硬件级功耗估计而进行。

公开(公告)号：US08786080B2

公开(公告)日：2014-07-22

申请号：US13046247

申请日：2011-03-11

申请人： Chooi Pei Lim ,  Jordan Plofsky ,  Yee Liang Tan ,  Teik Tiong Toong

发明人： Chooi Pei Lim ,  Jordan Plofsky ,  Yee Liang Tan ,  Teik Tiong Toong

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/60 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die.

摘要翻译： 描述了包括输入/​​输出（I / O）堆栈和用于制造这样的系统的方法的系统。 在一个实施方式中，这些方法包括堆叠包括I / O元件并排除逻辑元件的I / O管芯。 同样在一个实现中，所述方法还包括相对于I / O管芯堆叠集成电路管芯。 集成电路包括逻辑元件，不包括I / O元件。 I / O管芯与集成电路管芯的分离提供了各种好处，例如每个管芯的独立开发和I / O管芯I / O管脚上的I / O元件的空间相对于I / O管芯的I / O元件 在常规的模具中。 空间的增加允许集成电路管芯的新工艺生成，其中越来越多的逻辑元件安装在集成电路管芯的衬底的相同表面区域内。

公开(公告)号：US07143368B1

公开(公告)日：2006-11-28

申请号：US10866391

申请日：2004-06-10

申请人： Jordan Plofsky ,  Philippe Molson ,  Francois Pequillat

发明人： Jordan Plofsky ,  Philippe Molson ,  Francois Pequillat

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Power consumption estimation is performed at the system level in a design process, thus allowing early evaluation of feasibility and other considerations relating to logic/DSP design and hardware implementation of a proposed electronic design. Evaluation of the system level power consumption estimate(s) permits adjustment of a system level representation of the proposed electronic design, prior to investment of substantial resources in the electronic design. Other estimates, including other power consumption estimates, may be performed to adjust the proposed electronic design as well. Such estimates may be made in response to gate level power consumption estimates and/or hardware level power consumption estimates.

公开(公告)号：US20120228760A1

公开(公告)日：2012-09-13

申请号：US13046247

申请日：2011-03-11

申请人： Chooi Pei Lim ,  Jordan Plofsky ,  Yee Liang Tan ,  Teik Tiong Toong

发明人： Chooi Pei Lim ,  Jordan Plofsky ,  Yee Liang Tan ,  Teik Tiong Toong

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L25/0657 ,  H01L23/60 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die.

摘要翻译： 描述了包括输入/​​输出（I / O）堆栈和用于制造这样的系统的方法的系统。 在一个实施方式中，这些方法包括堆叠包括I / O元件并排除逻辑元件的I / O管芯。 同样在一个实现中，所述方法还包括相对于I / O管芯堆叠集成电路管芯。 集成电路包括逻辑元件，不包括I / O元件。 I / O管芯与集成电路管芯的分离提供了各种好处，例如每个管芯的独立开发和I / O管芯I / O管脚上的I / O元件的空间相对于I / O管芯的I / O元件 在常规的模具中。 空间的增加允许集成电路管芯的新工艺生成，其中越来越多的逻辑元件安装在集成电路管芯的衬底的相同表面区域内。

公开(公告)号：US07539900B1

公开(公告)日：2009-05-26

申请号：US10629508

申请日：2003-07-29

申请人： Jordan Plofsky

发明人： Jordan Plofsky

IPC分类号： G06F11/00

CPC分类号： G06F11/27 ,  G01R31/31705 ,  G11C29/16 ,  G11C29/56

摘要： A technique for embedding a microprocessor into an integrated circuit allows on-chip testing and debugging. The microprocessor present on the chip tests and debugs the rest of the chip. Both testing and debugging of a programmable logic device use an embedded microprocessor. Testing is performed by the device manufacturer using a test system. Debugging is performed by a user using a host computer. A PLD includes programmable logic, an embedded microprocessor and separate memory. Testing or debugging routines, patterns, simulations, etc., are downloaded onto the memory. The microprocessor executes the test or debug routine and uploads results to the test system or host computer. The technique is applicable any integrated circuit that can include an embedded microprocessor and associated memory, such as a PLD, an ASIC, a memory chip, or an analog chip.

摘要翻译： 将微处理器嵌入集成电路的技术允许片上测试和调试。 芯片上的微处理器测试并调试芯片的其余部分。 可编程逻辑器件的测试和调试都使用嵌入式微处理器。 测试由设备制造商使用测试系统执行。 调试由使用主机的用户执行。 PLD包括可编程逻辑，嵌入式微处理器和单独的存储器。 测试或调试程序，模式，模拟等都被下载到内存中。 微处理器执行测试或调试例程，并将结果上传到测试系统或主机。 该技术适用于可以包括嵌入式微处理器和相关存储器（例如PLD，ASIC，存储器芯片或模拟芯片）的任何集成电路。

公开(公告)号：US07062685B1

公开(公告)日：2006-06-13

申请号：US10317436

申请日：2002-12-11

申请人： Jordan Plofsky ,  Jayabrata Ghosh Dastidar ,  Michael Harms

发明人： Jordan Plofsky ,  Jayabrata Ghosh Dastidar ,  Michael Harms

IPC分类号： G06F11/00

CPC分类号： G01R31/318516 ,  G06F11/1423 ,  H03K19/177 ,  H03K19/17736

摘要： Techniques for monitoring the performance of a programmable circuit and to provide an early warning of a potential failure are provided. A processor monitors the performance of components on a programmable circuit over time. The processor stores performance characteristics for the components in memory. If the performance characteristics for particular components fall outside tolerance ranges, these components may to fail to operate according to specifications. Once the performance characteristics for particular components are outside the tolerance ranges, the processor sends out an alert signal. The alert signal indicates the possibility that the performance of the programmable circuit may violate the specifications in the future. The processor may repair the programmable circuit by re-routing around the problem components.

摘要翻译： 提供了用于监视可编程电路的性能并提供潜在故障的早期警告的技术。 处理器随时间监视可编程电路上的组件的性能。 处理器存储内存中组件的性能特征。 如果特定部件的性能特性落在公差范围之外，这些部件可能无法根据规格进行操作。 一旦特定组件的性能特征超出公差范围，处理器就会发出警报信号。 警报信号表示可编程电路的性能可能会违反将来的规格。 处理器可以通过围绕问题组件重新路由来修复可编程电路。