利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.045 秒)

    Process of operating a processor with domains and clocks
    1.
    发明授权
    Process of operating a processor with domains and clocks 失效
    使用域和时钟操作处理器的过程

    公开(公告)号：US06760866B2

    公开(公告)日：2004-07-06

    申请号：US10336986

    申请日：2003-01-06

    申请人： Gary L. Swoboda ,  Martin D. Daniels

    发明人： Gary L. Swoboda ,  Martin D. Daniels

    IPC分类号： G06F1100

    CPC分类号： G06F9/3005 ,  G06F9/30087 ,  G06F11/3696

    摘要： A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

    摘要翻译： 一种形成在单个半导体芯片中的数据处理装置。 该数据处理装置包括一个电子处理器，以及通常一起操作的片上外设电路。 还包括用于选择性地将外部提供的数据输入到电子处理器和片上外围电路中的装置，用于在仿真操作模式下彼此独立地启动和停止电子处理器和片上外围电路的操作。

    Devices, systems and methods for mode driven stops
    2.
    发明授权
    Devices, systems and methods for mode driven stops 失效
    用于模式驱动停止的设备，系统和方法

    公开(公告)号：US06349392B1

    公开(公告)日：2002-02-19

    申请号：US09353520

    申请日：1999-07-14

    申请人： Gary L. Swoboda ,  Martin D. Daniels

    发明人： Gary L. Swoboda ,  Martin D. Daniels

    IPC分类号： G06F1100

    CPC分类号： G06F11/261 ,  G06F11/267

    摘要： A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

    摘要翻译： 一种形成在单个半导体芯片中的数据处理装置。 该数据处理装置包括一个电子处理器，以及通常一起操作的片上外设电路。 还包括用于选择性地将外部提供的数据输入到电子处理器和片上外围电路中的装置，用于在仿真操作模式下彼此独立地启动和停止电子处理器和片上外围电路的操作。

    Logic circuits systems, and methods having individually testable logic modules
    3.
    发明授权
    Logic circuits systems, and methods having individually testable logic modules 失效
    逻辑电路系统和具有可单独测试的逻辑模块的方法

    公开(公告)号：US5173904A

    公开(公告)日：1992-12-22

    申请号：US717170

    申请日：1991-06-17

    申请人： Martin D. Daniels ,  Derek Roskell

    发明人： Martin D. Daniels ,  Derek Roskell

    IPC分类号： G01R31/3185 ,  G06F11/26 ,  G06F11/36

    CPC分类号： G06F11/261 ,  G01R31/318536 ,  G01R31/318558

    摘要： A modular logic circuit is disclosed, where each of the modules may be selected for testing by means of a scan path within the module made up of serial register latches (SRLs), each SRL being connected to predetermined nodes in the module functional circuitry. Each of the modules has a test port, which is independent from the system bus interconnections in the logic circuit, and which has an SRL for receiving serial data for selection of the scan path within the module. Responsive to the logic state stored in a module's selection SRL, the scan path within the module will either be enabled or disabled. After selection of a module or modules for testing, serial data is scanned into the SRLs in the scan path for setting the associated predetermined functional circuitry nodes; after exercise of the functional circuitry, the SRLs in the scan path store the results of the exercise at the predetermined nodes. An additional SRL is contained within each test port, and in the scan path, for storing a logic state corresponding to whether the functional circuitry in the module is to be connected to or disconnected from the system bus during the test sequence. A configuration is further disclosed which has global SRLs in the modules; such global SRLs are always in the scan path, regardless of whether or not the module containing them is selected. Multiplexing of the scan data and the configuration data is also disclosed.

    摘要翻译： 公开了一种模块化逻辑电路，其中可以通过由串行寄存器锁存器（SRL）构成的模块内的扫描路径来选择每个模块进行测试，每个SRL连接到模块功能电路中的预定节点。 每个模块都有一个测试端口，它独立于逻辑电路中的系统总线互连，并具有一个SRL，用于接收用于选择模块内扫描路径的串行数据。 响应于存储在模块选择SRL中的逻辑状态，模块中的扫描路径将被启用或禁用。 在选择用于测试的模块或模块之后，将串行数据扫描到扫描路径中的SRL中以设置相关联的预定功能电路节点; 在运行功能电路之后，扫描路径中的SRL将锻炼的结果存储在预定节点处。 在每个测试端口中包含一个额外的SRL，并且在扫描路径中，用于存储对应于在测试序列期间模块中的功能电路是否连接到系统总线或从系统总线断开的逻辑状态。 进一步公开了在模块中具有全局SRL的配置; 这样的全局SRL始终位于扫描路径中，而不管是否选择了包含它们的模块。 还公开了扫描数据和配置数据的复用。

    IC with selectively applied functional and test clocks
    4.
    发明授权
    IC with selectively applied functional and test clocks 失效
    IC有选择地应用功能和测试时钟

    公开(公告)号：US06539497B2

    公开(公告)日：2003-03-25

    申请号：US09938201

    申请日：2001-08-22

    申请人： Gary L. Swoboda ,  Martin D. Daniels

    发明人： Gary L. Swoboda ,  Martin D. Daniels

    IPC分类号： G06F1100

    CPC分类号： G06F11/261 ,  G06F11/27

    摘要： A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

    摘要翻译： 一种形成在单个半导体芯片中的数据处理装置。 该数据处理装置包括一个电子处理器，以及通常一起操作的片上外设电路。 还包括用于选择性地将外部提供的数据输入到电子处理器和片上外围电路中的装置，用于在仿真操作模式下彼此独立地启动和停止电子处理器和片上外围电路的操作。

    Logic circuit having individually testable logic modules
    6.
    发明授权
    Logic circuit having individually testable logic modules 失效
    逻辑电路具有可单独测试的逻辑模块

    公开(公告)号：US4860290A

    公开(公告)日：1989-08-22

    申请号：US57078

    申请日：1987-06-02

    申请人： Martin D. Daniels ,  Derek Roskell

    发明人： Martin D. Daniels ,  Derek Roskell

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/26 ,  G06F11/36

    CPC分类号： G06F11/261 ,  G01R31/318536 ,  G01R31/318558

    摘要： A modular logic circuit is disclosed, where each of the modules may be selected for testing by means of a scan path within the module made up of serial register latches (SRLs), each SRL being connected to predetermined nodes in the module functional circuitry. Each of the modules has a test port, which is independent from the system bus interconnections in the logic circuit, and which has an SRL for receiving serial data for selection of the scan path within the module. Responsive to the logic state stored in a module's selection SRL, the scan path within the module will either be enabled or disabled. After selection of a module or modules for testing, serial data is scanned into the SRLs in the scan path for setting the associated predetermined functional circuitry nodes; after exercise of the functional circuitry, the SRLs in the scan path store the results of the exercise at the predetermined nodes. An additional SRL is contained within each test port, and in the scan path, for storing a logic state corresponding to whether the functional circuitry in the module is to be connected to or disconnected from the system bus during the test sequence. A configuration if further disclosed which has global SRLs in the modules; such global SRLs are always in the scan path, regardless of whether or not the module containing them is selected. Multiplexing of the scan data and the configuration data is also disclosed.

    摘要翻译： 公开了一种模块化逻辑电路，其中可以通过由串行寄存器锁存器（SRL）构成的模块内的扫描路径来选择每个模块进行测试，每个SRL连接到模块功能电路中的预定节点。 每个模块都有一个测试端口，它独立于逻辑电路中的系统总线互连，并具有一个SRL，用于接收用于选择模块内扫描路径的串行数据。 响应于存储在模块选择SRL中的逻辑状态，模块中的扫描路径将被启用或禁用。 在选择用于测试的模块或模块之后，将串行数据扫描到扫描路径中的SRL中以设置相关联的预定功能电路节点; 在运行功能电路之后，扫描路径中的SRL将锻炼的结果存储在预定节点处。 在每个测试端口中包含一个额外的SRL，并且在扫描路径中，用于存储对应于在测试序列期间模块中的功能电路是否连接到系统总线或从系统总线断开的逻辑状态。 如果进一步披露了在模块中具有全局SRL的配置; 这样的全局SRL始终位于扫描路径中，而不管是否选择了包含它们的模块。 还公开了扫描数据和配置数据的复用。

    Parallel/serial scan system for testing logic circuits
    7.
    发明授权
    Parallel/serial scan system for testing logic circuits 失效
    用于测试逻辑电路的并行/串行扫描系统

    公开(公告)号：US4710933A

    公开(公告)日：1987-12-01

    申请号：US790569

    申请日：1985-10-23

    申请人： Theo J. Powell ,  Jeffrey D. Bellay ,  Martin D. Daniels ,  Yin-Chao Hwang

    发明人： Theo J. Powell ,  Jeffrey D. Bellay ,  Martin D. Daniels ,  Yin-Chao Hwang

    IPC分类号： G01R31/3185 ,  G01R31/28

    CPC分类号： G01R31/318558

    摘要： A testable logic circuit includes parallel registers (72)-(80) for interfacing with a common internal bus (70). The parallel registers (72)-(80) are individually addressable by an address decoder (104) for storage of test vectors therein. These test vectors are then applied to associated logic circuits. Individual shift register latches (92)-(102) are provided at imbedded locations therein. The shift register latches are interfaced with a serial data link to allow serial loading of data therein. The parallel latches function in both the test mode to store test vectors for application to the associated logic and also in the operational mode for storage of logic data. Use of parallel registers increases the speed at which data is scanned into the device.

    摘要翻译： 可测试逻辑电路包括用于与公共内部总线（70）接口的并行寄存器（72） - （80）。 并行寄存器（72） - （80）可以由地址解码器（104）单独寻址，用于在其中存储测试向量。 然后将这些测试矢量应用于相关联的逻辑电路。 在其中的嵌入位置处提供单独的移位寄存器锁存器（92） - （102）。 移位寄存器锁存器与串行数据链路连接，以允许在其中串行加载数据。 并行锁存器在测试模式下都能起作用，用于存储用于应用于相关逻辑的测试向量，以及存储逻辑数据的操作模式。 并行寄存器的使用增加了数据扫描到器件中的速度。

    Level sensitive latch stage
    8.
    发明授权
    Level sensitive latch stage 失效
    电平敏感锁定级

    公开(公告)号：US4667339A

    公开(公告)日：1987-05-19

    申请号：US557783

    申请日：1983-12-05

    申请人： Graham S. Tubbs ,  Martin D. Daniels ,  Robert Schaaf ,  Ronald Walther

    发明人： Graham S. Tubbs ,  Martin D. Daniels ,  Robert Schaaf ,  Ronald Walther

    IPC分类号： G06F3/05 ,  G11C19/28 ,  H03K3/037 ,  H03M1/12 ,  G11C11/34

    CPC分类号： G11C19/28

    摘要： A logic circuit that has a plurality of stages that are driven by a clock source that provides at least 2 clock signals and includes at least a single latch stage located between two of the plurality of stages is configured with field effect transistor technology. The latch stage includes an isolation means for isolating the preceding circuit of the plurality of stages from flow-through of the clocks and signals that are connected to the latch stage, and a latch circuit for storing the data that is applied to the latch stage between clock pulses. A plurality of latch stages can easily be configured as a shift register latch.

    摘要翻译： 具有由提供至少2个时钟信号并且包括位于多个级之间的至少一个锁存级的时钟源驱动的多级的逻辑电路被配置为场效应晶体管技术。 锁存级包括用于隔离多个级的先前电路与连接到锁存级的时钟和信号的流通的隔离装置，以及用于存储施加到锁存级之间的数据的锁存电路， 时钟脉冲。 多个锁存级可以容易地配置为移位寄存器锁存器。

    Data processing devices, systems and methods with mode driven stops
    10.
    发明授权
    Data processing devices, systems and methods with mode driven stops 失效
    具有模式驱动停止的数据处理设备，系统和方法

    公开(公告)号：US6085336A

    公开(公告)日：2000-07-04

    申请号：US827549

    申请日：1992-01-29

    申请人： Gary L. Swoboda ,  Martin D. Daniels

    发明人： Gary L. Swoboda ,  Martin D. Daniels

    IPC分类号： G06F11/00

    CPC分类号： G06F11/00 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/318594 ,  G01R31/319 ,  G06F11/263

    摘要： A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

    摘要翻译： 一种形成在单个半导体芯片中的数据处理装置。 该数据处理装置包括一个电子处理器，以及通常一起操作的片上外设电路。 还包括用于选择性地将外部提供的数据输入到电子处理器和片上外围电路中的装置，用于在仿真操作模式下彼此独立地启动和停止电子处理器和片上外围电路的操作。