公开(公告)号：US07049225B2

公开(公告)日：2006-05-23

申请号：US10782783

申请日：2004-02-23

申请人： Ju-Bum Lee

发明人： Ju-Bum Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76837 ,  H01L21/76895 ,  H01L21/76897

摘要： In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures are filled with a first insulation film, etch stop film patterns having a width which is wider than that of the structures are formed on the structures. A second insulation film is formed to cover the resultant structures without voids between the structures.

摘要翻译： 在半导体器件的制造中，在包括导电图案和绝缘图案的结构的侧壁上形成间隔物。 绝缘图案比导电图案薄至少四倍。 在结构之间的间隙填充有第一绝缘膜之后，在结构上形成具有比结构宽的宽度的蚀刻停止膜图案。 形成第二绝缘膜以覆盖结构之间没有空隙的所得结构。

公开(公告)号：US06982223B2

公开(公告)日：2006-01-03

申请号：US10413944

申请日：2003-04-15

申请人： Ju-Wan Kim ,  Shin-Hye Kim ,  Ju-Bum Lee ,  Hyong-Soo Kim

发明人： Ju-Wan Kim ,  Shin-Hye Kim ,  Ju-Bum Lee ,  Hyong-Soo Kim

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/02129 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/02337 ,  H01L21/31625 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76837

摘要： A method of manufacturing a semiconductor device by which a generation of a void is prevented after depositing an interlayer dielectric material. First, a plurality of conductive patterns are formed on a substrate and then, a capping insulation layer is formed on the conductive patterns. The capping insulation layer is treated with plasma, and an interlayer dielectric material is deposited on the plasma treated capping insulation layer. The dependency of the interlayer dielectric on the type of material and form of an underlying layer is reduced to improve a gap-filling characteristic, especially for a gap having a high aspect ratio. An improved gap-filling characteristic is accomplished and the formation of all or substantially all of the voids from forming in a gap is prevented even though an interlayer dielectric is deposited under a conventional deposition conditions.

摘要翻译： 一种制造半导体器件的方法，其中在沉积层间电介质材料之后防止产生空隙。 首先，在基板上形成多个导电图案，然后在导电图案上形成封盖绝缘层。 用等离子体处理封盖绝缘层，并且在等离子体处理的封盖绝缘层上沉积层间电介质材料。 层间电介质对材料类型和下层的形式的依赖性被降低以改善间隙填充特性，特别是对于具有高纵横比的间隙。 实现了改进的间隙填充特性，并且即使在常规沉积条件下沉积层间电介质，也可防止在间隙中形成全部或基本上所有空隙的形成。

公开(公告)号：US20050136686A1

公开(公告)日：2005-06-23

申请号：US11015095

申请日：2004-12-16

申请人： Do-Hyung Kim ,  Hyeon-Deok Lee ,  Ju-Bum Lee

发明人： Do-Hyung Kim ,  Hyeon-Deok Lee ,  Ju-Bum Lee

IPC分类号： H01L21/205 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L21/76 ,  H01L21/469

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/31612 ,  H01L21/76229 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76837

摘要： A method of filling gaps in an integrated circuit device is provided, that is less likely to fill voids and does not cause a lung defect. In one embodiment, a method of manufacturing an integrated circuit device including the gap filling method includes: etching a predetermined area of an integrated circuit device to form a trench, filling the trench with a high density plasma oxide by performing an HDP-CVD process using a first process gas including comprising a gas containing an element from the fluorine group, silane gas, and oxygen to form a high density plasma oxide layer, and plasma treating the integrated circuit substrate with a second process gas including a hydrogen gas or hydrogen and oxygen gases.

摘要翻译： 提供了一种填充集成电路装置中的间隙的方法，其不太可能填充空隙并且不引起肺部缺陷。 在一个实施例中，制造包括间隙填充方法的集成电路器件的方法包括：蚀刻集成电路器件的预定区域以形成沟槽，通过使用HDP-CVD工艺使用高密度等离子体氧化物填充沟槽 包括含有来自氟基团的元素的气体，硅烷气体和氧气以形成高密度等离子体氧化物层的第一工艺气体，以及用包括氢气或氢气和氧气的第二工艺气体等离子体处理集成电路衬底 气体。

公开(公告)号：US20050009293A1

公开(公告)日：2005-01-13

申请号：US10822378

申请日：2004-04-12

申请人： Hong-Rae Kim ,  Ju-Bum Lee ,  Min Kim

发明人： Hong-Rae Kim ,  Ju-Bum Lee ,  Min Kim

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/336

CPC分类号： H01L21/76229

摘要： Methods of forming trench isolations are provided. A method includes providing a semiconductor substrate having a cell array region and a peripheral region. At least one cell trench in the cell array region and at least one peripheral trench wider than the cell trench in the peripheral region of the substrate are formed. The cell and the peripheral trenches have sidewalls. A first dielectric layer that partially fills the cell and peripheral trenches is formed over the substrate. At least one photoresist pattern that exposes at least the cell trench partially filled with the first dielectric layer is formed over the substrate. The first dielectric layer formed on the sidewalls of the exposed cell trench is etched by using the photoresist pattern as a etch mask. Subsequently, the photoresist pattern is removed. A second dielectric layer filling the cell and peripheral trenches is formed over the substrate where the photoresist pattern is removed.

摘要翻译： 提供了形成沟槽隔离的方法。 一种方法包括提供具有单元阵列区域和周边区域的半导体衬底。 形成电池阵列区域中的至少一个电池沟道和比衬底的周边区域中的电池沟槽宽的至少一个外围沟槽。 电池和外围沟槽具有侧壁。 部分填充电池和外围沟槽的第一电介质层形成在衬底上。 在衬底上形成至少一个曝光至少部分填充有第一介电层的单元沟道的光致抗蚀剂图案。 通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻形成在暴露的单元沟槽的侧壁上的第一介电层。 随后，去除光致抗蚀剂图案。 在衬底上形成填充电池和外围沟槽的第二电介质层，其中光致抗蚀剂图案被去除。

公开(公告)号：US06762126B2

公开(公告)日：2004-07-13

申请号：US10082019

申请日：2002-02-20

申请人： Young-Joo Cho ,  Eun-Kee Hong ,  Ju-Bum Lee

发明人： Young-Joo Cho ,  Eun-Kee Hong ,  Ju-Bum Lee

IPC分类号： H01L21311

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02318 ,  H01L21/02337 ,  H01L21/3125

摘要： In a method for forming an interlayer dielectric film, an insulating film is deposited on a semiconductor substrate that has a metal wiring pattern. The insulating film is polished by CMP until exposing an upper portion of the wiring pattern. A spin on glass composition, which includes polysilazane, is coated over the polished insulating material and exposed portions of the wiring pattern to form a film. The film is then pre-baked in a temperature range of 50 to 350° C., and then hard-baked in a temperature range of 300 to 500° C. After the hard-baking, the film is then heat-treated in an oxidation atmosphere. With the hard-baking, gasses of the coating of film may be removed so that the amount of gas generated during a subsequent anneal or heat-treating process may be reduced. Accordingly, particle contaminants may be reduced by such process in addition to providing a means for reduced risk of crack formation.

摘要翻译： 在形成层间电介质膜的方法中，在具有金属布线图案的半导体基板上沉积绝缘膜。 通过CMP抛光绝缘膜，直到暴露布线图案的上部。 包括聚硅氮烷在内的旋涂玻​​璃组合物涂覆在抛光的绝缘材料上并且布线图案的暴露部分形成膜。 然后将膜在50〜350℃的温度范围内进行预烘烤，然后在300〜500℃的温度范围内进行硬烘烤。在硬烘烤后，将膜进行热处理 氧化气氛。 通过硬烘烤，可以除去膜涂层的气体，从而可以减少在随后的退火或热处理过程中产生的气体的量。 因此，除了提供降低裂纹风险的方法之外，还可以通过这种方法减少颗粒污染物。

公开(公告)号：US5670400A

公开(公告)日：1997-09-23

申请号：US575876

申请日：1995-12-21

申请人： Joo-Hyung Lee ,  Ju-Bum Lee ,  Jae-Hyung Lee

发明人： Joo-Hyung Lee ,  Ju-Bum Lee ,  Jae-Hyung Lee

IPC分类号： G02F1/136 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L21/786

CPC分类号： H01L29/4908 ,  H01L21/28158 ,  H01L29/42384

摘要： A dual gate insulating film of a thin film transistor (TFT) is disclosed in which edge-thinning is eliminated by forming a thermal oxide film after depositing an oxide film by a low temperature chemical vapor deposition (CVD) method. According to the disclosed dual gate insulating film and method for making the same, exposure of gate material on edges of the gate film is prevented, grooving of the active pattern of polycrystalline silicon is reduced, and the same electric and insulating characteristics as those of the conventional thermal oxide film are obtained.

摘要翻译： 公开了薄膜晶体管（TFT）的双栅极绝缘膜，其中通过在低温化学气相沉积（CVD）方法沉积氧化膜之后形成热氧化膜来消除边缘薄化。 根据所公开的双栅极绝缘膜及其制造方法，防止栅极材料在栅极膜的边缘上的暴露，多晶硅的有源图案的切槽减小，并且具有与 得到常规的热氧化膜。

公开(公告)号：US20080020594A1

公开(公告)日：2008-01-24

申请号：US11827777

申请日：2007-07-13

申请人： Do-Hyung Kim ,  Ju-Bum Lee

发明人： Do-Hyung Kim ,  Ju-Bum Lee

IPC分类号： H01L21/31

CPC分类号： H01L45/1683 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

摘要： In a method of manufacturing a phase-changeable memory device, a lower electrode is formed on a substrate. Silicon oxynitride is then deposited on the lower electrode at a temperature of about 450° C. to about 650° C. to form an insulating interlayer that is relatively dense on the lower electrode. The insulating interlayer is partially etched to form a contact hole exposing the lower electrode. A phase-changeable material layer pattern filling up the contact hole is formed on the insulating interlayer such that the phase-changeable material layer pattern makes contact with the lower electrode.

摘要翻译： 在制造相变存储器件的方法中，在基片上形成下电极。 然后在约450℃至约650℃的温度下将氮氧化硅沉积在下电极上，以形成在下电极上相对致密的绝缘中间层。 部分地蚀刻绝缘中间层以形成暴露下电极的接触孔。 在绝缘中间层上形成填充接触孔的相变材料层图案，使得相变材料层图案与下电极接触。

公开(公告)号：US07125774B2

公开(公告)日：2006-10-24

申请号：US10937532

申请日：2004-09-08

申请人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

发明人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/3205

CPC分类号： H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

摘要翻译： 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

公开(公告)号：US20060073669A1

公开(公告)日：2006-04-06

申请号：US11245367

申请日：2005-10-05

申请人： Shin-Hye Kim ,  Ju-Bum Lee ,  Min Kim

发明人： Shin-Hye Kim ,  Ju-Bum Lee ,  Min Kim

IPC分类号： H01L21/20

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

摘要： In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the first insulation interlayer and the pad. A contact hole exposing at least a portion of the contact pad is formed by partially etching the second insulation interlayer and the etch stop layer. A preliminary lower electrode is formed in the hole. The preliminary lower electrode is isotropically etched to form a lower electrode contacting the contact pad. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

摘要翻译： 在一个实施例中，为了制造半导体器件，在衬底上形成第一绝缘中间层。 通过第一绝缘夹层形成接触垫。 在第一绝缘夹层和衬垫上依次形成蚀刻停止层和第二绝缘中间层。 通过部分蚀刻第二绝缘夹层和蚀刻停止层来形成暴露接触焊盘的至少一部分的接触孔。 在孔中形成初级下电极。 预备下电极被各向同性地蚀刻以形成接触接触垫的下电极。 电介质层和上电极依次形成在下电极上。

公开(公告)号：US20050054163A1

公开(公告)日：2005-03-10

申请号：US10937532

申请日：2004-09-08

申请人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

发明人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

摘要翻译： 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。