公开(公告)号：US5225037A

公开(公告)日：1993-07-06

申请号：US709954

申请日：1991-06-04

申请人： Richard A. Elder ,  Arthur M. Wilson ,  Susan V. Bagen ,  Juanita G. Miller

发明人： Richard A. Elder ,  Arthur M. Wilson ,  Susan V. Bagen ,  Juanita G. Miller

IPC分类号： G01R1/073

CPC分类号： G01R1/0735

摘要： A flexible polyimide film is used to support an array of precisely located contact bumps which are used to probe die on a wafer of semiconductor circuits, or an unmounted integrated circuit die, several integrated circuits, or hybrid devices. By utilizing a standard I/O contact pattern for the flexible film and fabricating the membrane assembly of interconnects on an aluminum substrate, it is possible to produce a more reliable probe card, while reducing the fabrication time and costs for the probe card. The polyimide film must be selected to have a CTE of 3 to 5, which is only about 1/5 to 1/7 as great as the CTE of the aluminum substrate on which the film is formed. This produces a critical degree of compressive stress in the polyimide film, and a resulting "bow" of the film when the central area of the aluminum is etched away.

摘要翻译： 柔性聚酰亚胺膜用于支撑用于在半导体电路的晶片或未安装的集成电路管芯，多个集成电路或混合器件上探测管芯的精确定位的接触凸块阵列。 通过利用柔性膜的标准I / O接触图案和在铝基板上制造互连膜组件，可以产生更可靠的探针卡，同时减少探针卡的制造时间和成本。 必须选择聚酰亚胺膜的CTE为3〜5，与形成有膜的铝基板的CTE相比，仅为1/5〜1/7左右。 这在聚酰亚胺膜中产生临界程度的压缩应力，并且当铝的中心区域被蚀刻掉时，所得到的“弓”。

公开(公告)号：US06613700B2

公开(公告)日：2003-09-02

申请号：US09998075

申请日：2001-11-30

申请人： David C. Hall ,  Juanita G. Miller

发明人： David C. Hall ,  Juanita G. Miller

IPC分类号： H01L2131

CPC分类号： H01L21/02282 ,  B05D1/005 ,  H01L21/02118 ,  H01L21/312

摘要： A method for spin coating high viscosity materials. Two dispense steps are used. The first dispense step dispenses a small amount (102) of high viscosity material at the center of the wafer (100). A high-speed wafer rotation spreads the material to form a thin layer (104) to prime the surface of the wafer (100) and lower the surface tension without regard to uniformity. A second dispense step occurs at lower RPM and coats (108) the wafer (100) more uniformly.

公开(公告)号：US5646068A

公开(公告)日：1997-07-08

申请号：US384506

申请日：1995-02-03

申请人： Arthur M. Wilson ,  Mark A. Kressley ,  Dean L. Frew ,  Juanita G. Miller ,  John E. Hanicak ,  Philip E. Hecker ,  James M. Drumm

发明人： Arthur M. Wilson ,  Mark A. Kressley ,  Dean L. Frew ,  Juanita G. Miller ,  John E. Hanicak ,  Philip E. Hecker ,  James M. Drumm

IPC分类号： H01L21/48 ,  H01L21/60 ,  H01L21/68 ,  H01L23/498 ,  H01L25/065 ,  H05K3/34 ,  H01L21/44

CPC分类号： H01L24/12 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/11 ,  H01L25/0652 ,  H05K3/3473 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/043 ,  H05K2203/0726

摘要： A method of making a microelectronic circuit and the connection pattern therefor including the steps of providing a substrate (3), preferably silicon and preferably including a layer of nickel (38) under a layer of gold (36) thereon. Regions are formed on the substrate for connection of electrical components to the substrate using a first metallurgy, preferably gold and a pattern of bumps (5, 7) is formed of a second metallurgy different from the first metallurgy, preferably lead/tin solder. An interconnection pattern is formed on the substrate contacting at least one bump and at least one pad. The pattern of solder bumps is formed by providing a coupon (31) and patterning the bumps on the coupon and applied to the substrate while attached to the coupon, then heated to cause flow of the bumps onto the substrate. The coupon is then removed from the bumps with the bumps remaining on the substrate. Electrical components are applied to the region of first metallurgy and electrically bonded by wire bonding or Tape Automated Bonding techniques. Electrical components are applied to the region of the second metallurgy and electrically bonded by flip-chip technique.

摘要翻译： 一种制造微电子电路的方法及其连接图案包括以下步骤：提供衬底（3），优选硅，并且优选地包括在其上的金层（36）下方的一层镍（38）。 区域形成在基板上，用于使用第一冶金将电气部件连接到基板，优选金和凸起图案（5,7）由不同于第一冶金，优选铅/锡焊料的第二冶金形成。 在与至少一个凸块和至少一个焊盘接触的衬底上形成互连图案。 焊料凸块的图案通过提供优惠券（31）并且在附件上图案化凸起并施加到基板上而形成，然后加热以使凸块流到基板上。 然后从凸块上取出试样，凸块残留在基片上。 电气部件应用于第一冶金领域，并通过引线接合或磁带自动键合技术进行电接合。 电气部件被施加到第二冶金的区域并通过倒装芯片技术电连接。

公开(公告)号：US5327327A

公开(公告)日：1994-07-05

申请号：US969602

申请日：1992-10-30

申请人： Dean L. Frew ,  Mark A. Kressley ,  Arthur M. Wilson ,  Juanita G. Miller ,  Philip E. Hecker, Jr. ,  James Drumm ,  Randall E. Johnson ,  Rick Elder

发明人： Dean L. Frew ,  Mark A. Kressley ,  Arthur M. Wilson ,  Juanita G. Miller ,  Philip E. Hecker, Jr. ,  James Drumm ,  Randall E. Johnson ,  Rick Elder

IPC分类号： H01L25/065 ,  H05K1/11

CPC分类号： H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2924/0002

摘要： The multi-chip circuit module of the invention comprises a plurality of circuit chips assembled in a laminated stack. Each chip includes a plurality of layers of thin film interconnect patterns in the normal configuration, except for the final layer or layers, which comprise a reroute pattern that locates all circuit input and output pads along a single edge of each chip. The relocated pads are provided with contact bumps to facilitate the addition of a bonded lead to each I/O pad extending therefrom to a point beyond the edge of each chip. Thus, upon lamination the protruding tips form an array of leads on a single lateral face of the laminated chip stack.

摘要翻译： 本发明的多芯片电路模块包括组装在层叠叠层中的多个电路芯片。 每个芯片包括正常配置中的多层薄膜互连图案，除了最终层或层，其包括沿着每个芯片的单个边缘定位所有电路输入和输出焊盘的重新布线图案。 重新定位的焊盘设置有接触凸块，以便于将结合引线添加到从其延伸到每个芯片边缘的点的每个I / O焊盘。 因此，在叠层时，突出的尖端在层压芯片堆叠的单个侧面上形成引线阵列。