公开(公告)号：US5672933A

公开(公告)日：1997-09-30

申请号：US550050

申请日：1995-10-30

Applicant: Arthur M. Wilson ,  Robert H. Taylor ,  Chi-Cheong Shen

Inventor： Arthur M. Wilson ,  Robert H. Taylor ,  Chi-Cheong Shen

IPC: H01J1/304 ,  H01J1/30

CPC classification number: H01J1/3042 ,  H01J2201/319

Abstract: An electron emitter plate (10, 10') for an FED image display has a gate conductive layer (22) spaced by a dielectric insulating layer (25) from a cathode conductive layer formed into a mesh (18). Arrays (12) of microtips (14) are located within mesh spacings (16) for field emission of electrons toward a phosphor layer (34) of an anode plate (11). Cathode layer (18) is patterned into column stripes (19) separated by gaps (17). Gate layer (22) is patterned into row cross-stripes (24) separated by gaps (23) which intersect with stripes (19) at matrix addressable pixel locations (30). Resistive layer (15) is patterned into stripes (40) separated by gaps (42) which interrupt column-to-column electrical communication through resistive layer (15). Unetched strips (43) are provided to bridge gap discontinuities for deposition of gate layer (22) at crossovers of rows (24) between columns (19). In one embodiment, gate layer (22) has a mesh pattern with apertured pads (46) commonly connected along resistive gap edges by marginal buses (50) formed on borders (49) of resistive layer (15) along gaps (42). Adjacent marginal buses (50) are connected by crossover buses (52) formed over bridging strips (43).

Abstract translation: 用于FED图像显示器的电子发射极板（10,10'）具有由形成为网状物（18）的阴极导电层与电介质绝缘层（25）隔开的栅极导电层（22）。 小尖头（14）的阵列（12）位于网格间隔（16）内，用于向阳极板（11）的荧光体层（34）发射电子。 阴极层（18）被图案化成由间隙（17）分开的列条纹（19）。 栅极层（22）被图案化成由在矩阵可寻址像素位置（30）处与条纹（19）相交的间隙（23）分开的行交叉条纹（24）。 电阻层（15）被图案化成由间隙（42）分开的条纹（40），间隙（42）通过电阻层（15）中断列对电连通。 提供未锯齿条（43）以桥接间隙不连续性，用于在柱（19）之间的行（24）的交叉处沉积栅极层（22）。 在一个实施例中，栅极层（22）具有网格图案，其中孔径焊盘（46）通过沿着间隙（42）形成在电阻层（15）的边界（49）上的边缘总线（50）沿着电阻性间隙边缘共同连接。 相邻边缘总线（50）通过形成在桥接条（43）上的交叉总线（52）连接。

公开(公告)号：US5646068A

公开(公告)日：1997-07-08

申请号：US384506

申请日：1995-02-03

Applicant: Arthur M. Wilson ,  Mark A. Kressley ,  Dean L. Frew ,  Juanita G. Miller ,  John E. Hanicak ,  Philip E. Hecker ,  James M. Drumm

Inventor： Arthur M. Wilson ,  Mark A. Kressley ,  Dean L. Frew ,  Juanita G. Miller ,  John E. Hanicak ,  Philip E. Hecker ,  James M. Drumm

IPC: H01L21/48 ,  H01L21/60 ,  H01L21/68 ,  H01L23/498 ,  H01L25/065 ,  H05K3/34 ,  H01L21/44

CPC classification number: H01L24/12 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/11 ,  H01L25/0652 ,  H05K3/3473 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/043 ,  H05K2203/0726

Abstract: A method of making a microelectronic circuit and the connection pattern therefor including the steps of providing a substrate (3), preferably silicon and preferably including a layer of nickel (38) under a layer of gold (36) thereon. Regions are formed on the substrate for connection of electrical components to the substrate using a first metallurgy, preferably gold and a pattern of bumps (5, 7) is formed of a second metallurgy different from the first metallurgy, preferably lead/tin solder. An interconnection pattern is formed on the substrate contacting at least one bump and at least one pad. The pattern of solder bumps is formed by providing a coupon (31) and patterning the bumps on the coupon and applied to the substrate while attached to the coupon, then heated to cause flow of the bumps onto the substrate. The coupon is then removed from the bumps with the bumps remaining on the substrate. Electrical components are applied to the region of first metallurgy and electrically bonded by wire bonding or Tape Automated Bonding techniques. Electrical components are applied to the region of the second metallurgy and electrically bonded by flip-chip technique.

Abstract translation: 一种制造微电子电路的方法及其连接图案包括以下步骤：提供衬底（3），优选硅，并且优选地包括在其上的金层（36）下方的一层镍（38）。 区域形成在基板上，用于使用第一冶金将电气部件连接到基板，优选金和凸起图案（5,7）由不同于第一冶金，优选铅/锡焊料的第二冶金形成。 在与至少一个凸块和至少一个焊盘接触的衬底上形成互连图案。 焊料凸块的图案通过提供优惠券（31）并且在附件上图案化凸起并施加到基板上而形成，然后加热以使凸块流到基板上。 然后从凸块上取出试样，凸块残留在基片上。 电气部件应用于第一冶金领域，并通过引线接合或磁带自动键合技术进行电接合。 电气部件被施加到第二冶金的区域并通过倒装芯片技术电连接。

公开(公告)号：US5557159A

公开(公告)日：1996-09-17

申请号：US341740

申请日：1994-11-18

Applicant: Robert H. Taylor ,  Kenneth G. Vickers ,  Bruce E. Gnade ,  Arthur M. Wilson ,  Charies E. Primm

Inventor： Robert H. Taylor ,  Kenneth G. Vickers ,  Bruce E. Gnade ,  Arthur M. Wilson ,  Charies E. Primm

IPC: H01J1/304 ,  H01J1/30 ,  H01J29/04

CPC classification number: H01J1/3042 ,  H01J2201/319

Abstract: The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70, illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90. Also disclosed is an arrangement of emitter clusters comprising conductive plates 102 having a plurality of microtip emitters 104 formed thereon, each cluster adjacent and laterally spaced from a stripe conductor 100 by a region 106 of a resistive material. The conductive stripes 100 are substantially parallel to each other, are spaced from one another by two conductive plates 102, and are joined by bus regions 110 outside the active area of the display.

Abstract translation: 场发射平板显示装置的发射极板60包括电阻材料层68和导电材料的网状结构62。 在由导体62的网格限定的间隔内，还在电阻涂层68的顶部形成导电板78.导电板78的上表面上形成了示意为锥体形状的微尖头发射体70。 通过它们与导电板78的电连接，所有微尖端发射器70将处于相等的电位。在一个实施例中，单个导电板82位于导体80的每个网格间隔内; 在另一个实施例中，四个导电板92对称地定位在导体90的每个网格间隔内。还公开了发射器​​簇的布置，其包括导电板102，其具有形成在其上的多个微尖端发射器104，每个簇相邻并且横向间隔开条带 导体100由电阻材料的区域106。 导电条100基本上彼此平行，通过两个导电板102彼此隔开，并且通过显示器的有效区域外的总线区域110连接。

公开(公告)号：US5327327A

公开(公告)日：1994-07-05

申请号：US969602

申请日：1992-10-30

Applicant: Dean L. Frew ,  Mark A. Kressley ,  Arthur M. Wilson ,  Juanita G. Miller ,  Philip E. Hecker, Jr. ,  James Drumm ,  Randall E. Johnson ,  Rick Elder

Inventor： Dean L. Frew ,  Mark A. Kressley ,  Arthur M. Wilson ,  Juanita G. Miller ,  Philip E. Hecker, Jr. ,  James Drumm ,  Randall E. Johnson ,  Rick Elder

IPC: H01L25/065 ,  H05K1/11

CPC classification number: H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2924/0002

Abstract: The multi-chip circuit module of the invention comprises a plurality of circuit chips assembled in a laminated stack. Each chip includes a plurality of layers of thin film interconnect patterns in the normal configuration, except for the final layer or layers, which comprise a reroute pattern that locates all circuit input and output pads along a single edge of each chip. The relocated pads are provided with contact bumps to facilitate the addition of a bonded lead to each I/O pad extending therefrom to a point beyond the edge of each chip. Thus, upon lamination the protruding tips form an array of leads on a single lateral face of the laminated chip stack.

Abstract translation: 本发明的多芯片电路模块包括组装在层叠叠层中的多个电路芯片。 每个芯片包括正常配置中的多层薄膜互连图案，除了最终层或层，其包括沿着每个芯片的单个边缘定位所有电路输入和输出焊盘的重新布线图案。 重新定位的焊盘设置有接触凸块，以便于将结合引线添加到从其延伸到每个芯片边缘的点的每个I / O焊盘。 因此，在叠层时，突出的尖端在层压芯片堆叠的单个侧面上形成引线阵列。

公开(公告)号：US5123850A

公开(公告)日：1992-06-23

申请号：US713039

申请日：1991-06-07

Applicant: Richard A. Elder ,  Randy Johnson ,  Dean L. Frew ,  Arthur M. Wilson

Inventor： Richard A. Elder ,  Randy Johnson ,  Dean L. Frew ,  Arthur M. Wilson

IPC: G01R1/04

CPC classification number: G01R1/0483

Abstract: Disclosed is a burn-in test socket which serves as a temporary package for integrated circuit die, multichip hybrid or a complete wafer without damaging the bonding pads or insulating passivation on the die during test and burn-in.

Abstract translation: 公开了一种老化测试插座，用作集成电路裸片，多芯片混合或完整晶片的临时封装，而不会在测试和老化期间损坏焊盘或绝缘钝化。

公开(公告)号：US4242698A

公开(公告)日：1980-12-30

申请号：US847956

申请日：1977-11-02

Applicant: Prabhakar B. Ghate ,  Arthur M. Wilson ,  Clyde R. Fuller

Inventor： Prabhakar B. Ghate ,  Arthur M. Wilson ,  Clyde R. Fuller

IPC: H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48

CPC classification number: H01L21/768 ,  H01L23/5226 ,  H01L2924/0002

Abstract: A microelectronic integrated circuit having first and second levels of thin-film metallization separated by an insulation layer is provided with a system for electrical interconnections between metallization levels, at selected locations, without requiring extra spacing between metal paths, in either the first or second levels. Maximum circuit density is thereby permitted, with no restriction on the placement of interconnection vias. Circuit layout is greatly simplified because all metal paths have uniform widths and minimum spacings, achieved with the use of vias that are "oversized" in both the transverse and longitudinal directions. Consequently, it is required that second level metal differ in composition from first level metal, and be patterned with an etchant that does not attack first level metal.

Abstract translation: 具有由绝缘层分离的第一和第二层薄膜金属化的微电子集成电路设置有用于在选定位置处的金属化水平之间的电互连的系统，而不需要金属路径之间的额外的间隔，在第一级或第二级 。 因此允许最大电路密度，而不限制互连通孔的放置。 电路布局大大简化，因为所有金属路径具有均匀的宽度和最小的间距，通过使用在横向和纵向方向上“过大”的通孔来实现。 因此，要求第二级金属的组成与第一级金属不同，并且用不侵蚀第一级金属的蚀刻剂进行图案化。

公开(公告)号：US5944975A

公开(公告)日：1999-08-31

申请号：US788149

申请日：1997-01-24

Applicant: Arthur M. Wilson ,  Chi-Cheong Shen ,  Saroja Ramamurthi

Inventor： Arthur M. Wilson ,  Chi-Cheong Shen ,  Saroja Ramamurthi

IPC: C23C28/00 ,  C25D5/02 ,  C25D5/10 ,  C25D5/54

CPC classification number: H01J9/025 ,  C25D5/022 ,  H01J1/3044 ,  H01J31/127 ,  H01J2329/0415

Abstract: A method of fabricating an emitter plate 12 for use in a field emission device comprising the steps of providing an insulating substrate 18 and forming a first conductive layer 13 on the insulating substrate 18. This is followed by the steps of forming an insulating layer 20 on the first conductive layer 13 and forming a second conductive layer 22 on the insulating layer 20. Then, a plurality of apertures 34 are formed through the second conductive layer 22 and through the insulating layer 20. A lift-off layer 36 is then formed on the second conductive layer 22. The lift-off layer 36 is formed by a plating process wherein the plating bath has a pH between 2.25 and 4.5, and current densities of 1 to 2O mA/cm.sup.2. The method may further comprise depositing conductive material through the plurality of apertures 34 to form a microtip 14 in each of the plurality of apertures 34. The excess deposited conductive material 14' and the lift-off layer 36 are then removed from the second conductive layer 22.

Abstract translation: 一种制造用于场发射器件的发射极板12的方法，包括以下步骤：在绝缘衬底18上提供绝缘衬底18并形成第一导电层13.其后是在绝缘衬底18上形成绝缘层20 第一导电层13并在绝缘层20上形成第二导电层22.然后，多个孔34穿过第二导电层22并通过绝缘层20形成。然后，将剥离层36形成在 第二导电层22.剥离层36通过电镀工艺形成，其中电镀浴的pH为2.25至4.5，电流密度为1至20mA / cm 2。 该方法还可以包括通过多个孔34沉积导电材料，以在多个孔34的每一个中形成微尖端14。然后将过量的沉积的导电材料14'和剥离层36从第二导电层 22。

公开(公告)号：US06251789B1

公开(公告)日：2001-06-26

申请号：US09464156

申请日：1999-12-16

Applicant: Arthur M. Wilson ,  Jody D. larsen

Inventor： Arthur M. Wilson ,  Jody D. larsen

IPC: H01L21302

CPC classification number: H01L21/7684 ,  H01L21/3212

Abstract: An embodiment of the instant invention is a method of fabricating a semiconductor device with a patterned dielectric layer having an upper surface and an opening with a bottom and sidewalls formed over a semiconductor substrate, the method comprising the steps of: forming a liner layer (layer 434 of FIGS. 1b-1d) on the upper surface of the patterned dielectric layer and on the bottom and the sidewalls of the opening in the patterned dielectric layer; forming a conductive layer (layer 436 of FIGS. 1b-1d) on the liner layer; removing the portion of the conductive layer which overlies the top surface of the dielectric layer thereby exposing a portion of the liner layer while leaving the portion of the conductive layer situated in the opening of the dielectric layer substantially unremoved, the step of removing the portion of the conductive layer is accomplished by chemical mechanical polishing using a first slurry; removing the exposed portion of the liner layer while leaving the unexposed portion of the liner layer substantially unremoved by chemical mechanical polishing using a second slurry; and wherein the first slurry removes the conductive layer much more readily than the liner layer and the second slurry removes the liner layer more readily than the conductive layer.

Abstract translation: 本发明的一个实施例是制造半导体器件的方法，该半导体器件具有图案化的介电层，其具有上表面和开口，底部和侧壁形成在半导体衬底上，该方法包括以下步骤：形成衬层（层 在图案化的介电层的上表面上，并且在图案化的介电层中的开口的底部和侧壁上， 在衬层上形成导电层（图1b-1d的层436）; 去除覆盖在电介质层的顶表面上的导电层的部分，从而暴露衬里层的一部分，同时使位于介质层的开口中的导电层的部分基本上不被移除，除去部分 导电层通过使用第一浆料的化学机械抛光来实现; 在通过使用第二浆料的化学机械抛光使衬里层的未曝光部分基本上不被除去时，去除衬里层的暴露部分; 并且其中所述第一浆料比所述衬里层更容易地除去所述导电层，并且所述第二浆料比所述导电层更容易地除去所述衬里层。

公开(公告)号：US5556316A

公开(公告)日：1996-09-17

申请号：US476776

申请日：1995-06-07

Applicant: Robert H. Taylor ,  Kenneth G. Vickers ,  Bruce E. Gnade ,  Arthur M. Wilson ,  Charles E. Primm

Inventor： Robert H. Taylor ,  Kenneth G. Vickers ,  Bruce E. Gnade ,  Arthur M. Wilson ,  Charles E. Primm

IPC: H01J31/12 ,  H01J1/30 ,  H01J1/304 ,  H01J9/02 ,  H01J9/18

CPC classification number: H01J1/3042 ,  H01J2201/319

Abstract: The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70, illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90. Also disclosed is an arrangement of emitter clusters comprising conductive plates 102 having a plurality of microtip emitters 104 formed thereon, or spaced therefrom by a thin layer of resistive material, each cluster adjacent and laterally spaced from a stripe conductor 100 by a region 106 of a resistive material. The conductive stripes 100 are substantially parallel to each other, are spaced from one another by two conductive plates 102, and are joined by bus regions 110 outside the active area of the display.

Abstract translation: 场发射平板显示装置的发射极板60包括电阻材料层68和导电材料的网状结构62。 在由导体62的网格限定的间隔内，还在电阻涂层68的顶部形成导电板78.导电板78的上表面上形成了示意为锥体形状的微尖头发射体70。 通过它们与导电板78的电连接，所有微尖端发射器70将处于相等的电位。在一个实施例中，单个导电板82位于导体80的每个网格间隔内; 在另一个实施例中，四个导电板92对称地定位在导体90的每个网格间隔内。还公开了发射器​​簇的布置，其包括导电板102，其具有形成在其上的多个微尖端发射器104，或者通过薄层 材料，每个簇通过电阻材料的区域106与条状导体100相邻和横向间隔开。 导电条100基本上彼此平行，通过两个导电板102彼此隔开，并且通过显示器的有效区域外的总线区域110连接。

公开(公告)号：US5536993A

公开(公告)日：1996-07-16

申请号：US378331

申请日：1995-01-26

Applicant: Robert H. Taylor ,  Kenneth G. Vickers ,  Bruce E. Gnade ,  Arthur M. Wilson ,  Charles E. Primm

Inventor： Robert H. Taylor ,  Kenneth G. Vickers ,  Bruce E. Gnade ,  Arthur M. Wilson ,  Charles E. Primm

IPC: H01J31/12 ,  H01J1/30 ,  H01J1/304 ,  H01J9/02

CPC classification number: H01J1/3042 ,  H01J2201/319

Abstract: The emitter plate 60 of a field emission flat panel display device includes a layer 68 of a resistive material and a mesh-like structure 62 of an electrically conductive material. A conductive plate 78 is also formed on top of resistive coating 68 within the spacing defined by the meshes of conductor 62. Microtip emitters 70; illustratively in the shape of cones, are formed on the upper surface of conductive plate 78. With this configuration, all of the microtip emitters 70 will be at an equal potential by virtue of their electrical connection to conductive plate 78. In one embodiment, a single conductive plate 82 is positioned within each mesh spacing of conductor 80; in another embodiment, four conductive plates 92 are symmetrically positioned within each mesh spacing of conductor 90. Also disclosed is an arrangement of emitter clusters comprising conductive plates 102 having a plurality of microtip emitters 104 formed thereon, or spaced therefrom by a thin layer of resistive material, each cluster adjacent and laterally spaced from a stripe conductor 100 by a region 106 of a resistive material. The conductive stripes 100 are substantially parallel to each other, are spaced from one another by two conductive plates 102, and are joined by bus regions 110 outside the active area of the display.

Abstract translation: 场发射平板显示装置的发射极板60包括电阻材料层68和导电材料的网状结构62。 导电板78也形成在由导体62的网格限定的间隔内的电阻涂层68的顶部上。微尖端发射器70; 在导电板78的上表面上形成了锥形的形状。利用这种结构，所有的微尖端发射器70由于与导电板78的电连接而处于相等的电位。在一个实施例中， 单导电板82位于导体80的每个网格间隔内; 在另一个实施例中，四个导电板92对称地定位在导体90的每个网格间隔内。还公开了发射器​​簇的布置，其包括导电板102，其具有形成在其上的多个微尖端发射器104，或者通过薄层 材料，每个簇通过电阻材料的区域106与条状导体100相邻和横向间隔开。 导电条100基本上彼此平行，通过两个导电板102彼此隔开，并且通过显示器的有效区域外的总线区域110连接。