公开(公告)号：US5968687A

公开(公告)日：1999-10-19

申请号：US196601

申请日：1998-11-20

申请人： Jui-Yu Chang ,  Chunshing Chen ,  Syun-Ming Jang ,  Ying-Ho Chen

发明人： Jui-Yu Chang ,  Chunshing Chen ,  Syun-Ming Jang ,  Ying-Ho Chen

IPC分类号： H01L23/544 ,  G03F9/00

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A mask pattern and method are described for the recovery of alignment marks on an integrated circuit wafer without the use of additional masks. The mask pattern and method provide means to recover the alignment marks after forming a metal layer on a planarized inter-level dielectric layer. The pattern which conventional methods have placed on a separate mask is formed in the end regions of a mask used for forming a pattern on the active region of the wafer. In order to fit the pattern in the end regions of the mask the pattern is divided into two parts. When the pattern is used to expose a layer of photoresist two exposure steps are used.

摘要翻译： 描述了用于在集成电路晶片上恢复对准标记的掩模图案和方法，而不使用附加掩模。 掩模图案和方法提供了在平坦化的层间电介质层上形成金属层之后恢复对准标记的装置。 在用于在晶片的有源区上形成图案的掩模的端部区域中形成常规方法已经放置在单独的掩模上的图案。 为了将图案装配在掩模的端部区域中，图案被分为两部分。 当使用图案曝光一层光致抗蚀剂时，使用两个曝光步骤。

公开(公告)号：US5858588A

公开(公告)日：1999-01-12

申请号：US850133

申请日：1997-05-01

申请人： Jui-Yu Chang ,  Chunshing Chen ,  Syun-Ming Jang ,  Ying-Ho Chen

发明人： Jui-Yu Chang ,  Chunshing Chen ,  Syun-Ming Jang ,  Ying-Ho Chen

IPC分类号： H01L23/544 ,  G03F9/00

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A mask pattern and method are described for the recovery of alignment marks on an integrated circuit wafer without the use of additional masks. The mask pattern and method provide means to recover the alignment marks after forming a metal layer on a planarized inter-level dielectric layer. The pattern which conventional methods have placed on a separate mask is formed in the end regions of a mask used for forming a pattern on the active region of the wafer. In order to fit the pattern in the end regions of the mask the pattern is divided into two parts. When the pattern is used to expose a layer of photoresist two exposure steps are used.

摘要翻译： 描述了用于在集成电路晶片上恢复对准标记的掩模图案和方法，而不使用附加掩模。 掩模图案和方法提供了在平坦化的层间电介质层上形成金属层之后恢复对准标记的装置。 在用于在晶片的有源区上形成图案的掩模的端部区域中形成常规方法已经放置在单独的掩模上的图案。 为了将图案装配在掩模的端部区域中，图案被分为两部分。 当使用图案曝光一层光致抗蚀剂时，使用两个曝光步骤。

公开(公告)号：US6043133A

公开(公告)日：2000-03-28

申请号：US121708

申请日：1998-07-24

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Jui-Yu Chang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Jui-Yu Chang ,  Chen-Hua Yu

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： The present invention provides a method of removing an shallow trench isolation (STI) oxide layer 38 from over alignment marks 30. The invention has two major features: (1) A STI photoresist mask 42A that is used to etch Alignment area trenches 34 around alignment marks 30 and to etch STI trenches 35 in device areas 14; and (2) A "reverse tone" STI photoresist mask 42B that is used to remove the isolation oxide 38 from over the alignment marks 30 and from over the active areas 37. The method begins by providing a substrate 10 having a device area 14, an alignment mark trench area 16; and an alignment mark area 18. A polish stop layer 20 22 is formed over the substrate 10. A trench isolation resist layer 42A is used to etch alignment area trenches 34 around the alignment marks 34 and STI trenches 35 in the device areas. A dielectric layer 38 is formed over the substrate. In a key step, the reverse tone trench isolation resist layer 42B is used to etch the first dielectric layer 38 from over the alignment marks 30 and the Active areas 27. Next, the remaining first dielectric layer 38 is chemical-mechanical polished thereby planarizing the first dielectric layer 38.

摘要翻译： 本发明提供从超过对准标记30去除浅沟槽隔离（STI）氧化物层38的方法。本发明具有两个主要特征：（1）STI光刻胶掩模42A，用于蚀刻对准区域沟槽34周围的对准 标记30并蚀刻设备区域14中的STI沟槽35; 和（2）用于从对准标记30上方和从有源区域37上方去除隔离氧化物38的“反向色调”STI光刻胶掩模42B。该方法开始于提供具有器件区域14的衬底10， 对准标记沟槽区域16; 和对准标记区域18.在衬底10上形成抛光阻挡层20 22.沟槽隔离抗蚀剂层42A用于蚀刻围绕器件区域中的对准标记34和STI沟槽35的对准区域沟槽34。 介电层38形成在衬底上。 在关键步骤中，反向色调沟槽隔离抗蚀剂层42B用于从对准标记30和有源区27上方蚀刻第一介电层38.接下来，剩余的第一介电层38进行化学机械抛光，从而平面化 第一电介质层38。

公开(公告)号：US5972798A

公开(公告)日：1999-10-26

申请号：US86775

申请日：1998-05-29

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US06444371B1

公开(公告)日：2002-09-03

申请号：US09377541

申请日：1999-08-19

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： G03F900

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US6020249A

公开(公告)日：2000-02-01

申请号：US891088

申请日：1997-07-10

申请人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： G03F9/00 ,  H01L23/544 ,  H01L23/48

CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

公开(公告)号：US5923996A

公开(公告)日：1999-07-13

申请号：US867312

申请日：1997-06-02

申请人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L23/544 ,  H01L21/46 ,  H01L21/301 ,  H01L21/78

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are followed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.

摘要翻译： 公开了一种用于在晶片的外周边形成对准标记的方法，其中它们在化学机械抛光（CMP）工艺期间不会受到很大的损害。 通过蚀刻将对准标记凹入衬底来提供完整的保护。 在同时完成凹槽蚀刻，同时遵循隔离沟以描绘器件区域。 因此，对准标记设置有保护凹槽而没有额外的步骤。 此外，通过在晶片的外周形成对准标记，通过提供用于集成电路的晶片面积的最大使用来提高生产率。

公开(公告)号：US6080635A

公开(公告)日：2000-06-27

申请号：US67262

申请日：1998-04-27

申请人： Syun-Ming Jang ,  Jui-Yu Chang

发明人： Syun-Ming Jang ,  Jui-Yu Chang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method of preserving alignment marks in integrated circuit substrates using shallow trench isolation after planarization using chemical mechanical polishing. A layer of silicon nitride is formed on the substrate and openings defining alignment trenches and isolation trenches are etched in the silicon nitride layer. Alignment trenches are formed in alignment regions of the substrate and isolation trenches are formed in the active region of the substrate during the same process step using the openings in the silicon nitride layer as a mask. A layer of dielectric is then deposited on the substrate filling the alignment trenches and the isolation trenches. The dielectric is then etched away from the alignment trenches and the substrate is planarized. After a layer of conducting material is deposited on the wafer the alignment trenches are preserved.

摘要翻译： 使用化学机械抛光在平坦化后使用浅沟槽隔离来在集成电路基板中保留对准标记的方法。 在衬底上形成氮化硅层，并且在氮化硅层中蚀刻限定对准沟槽和隔离沟槽的开口。 对准沟槽形成在衬底的对准区域中，并且在使用氮化硅层中的开口作为掩模的相同工艺步骤期间，在衬底的有源区域中形成隔离沟槽。 然后在填充对准沟槽和隔离沟槽的衬底上沉积电介质层。 然后将电介质蚀刻离开对准沟槽，并且将衬底平坦化。 在晶片上沉积一层导电材料之后，保留对准沟槽。

公开(公告)号：US07407601B2

公开(公告)日：2008-08-05

申请号：US10423569

申请日：2003-04-24

申请人： Shen-Nan Lee ,  Ying-Ho Chen ,  Syun-Ming Jang ,  Tzu-Jen Chou

发明人： Shen-Nan Lee ,  Ying-Ho Chen ,  Syun-Ming Jang ,  Tzu-Jen Chou

IPC分类号： C09K5/00

CPC分类号： C09G1/02 ,  C09K3/1409 ,  C09K3/1463 ,  H01L21/3212

摘要： A slurry system for a chemical mechanical polishing (CMP) process and a method for using the same wherein the slurry system includes an aqueous dispersion comprising at least abrasive polymer containing particles in an alkaline solution having a pH of less than about 9.5; and wherein the method includes providing a semiconductor wafer process surface including a oxide containing material and metal filled semiconductor features; providing the system; and, polishing in a CMP process the semiconductor wafer process surface using the slurry system to remove at least a portion of the oxide containing material and the metal comprising the metal filled semiconductor features.

摘要翻译： 用于化学机械抛光（CMP）方法的浆料系统及其使用方法，其中所述浆料系统包括含有至少含有在pH小于约9.5的碱性溶液中的含有颗粒的磨料聚合物的水分散体; 并且其中所述方法包括提供包括含氧化物材料和金属填充半导体特征的半导体晶片工艺表面; 提供系统; 并且在CMP工艺中使用浆料系统在半导体晶片工艺表面上抛光以去除含氧化物材料的至少一部分和包含金属填充的半导体特征的金属。

公开(公告)号：US06946397B2

公开(公告)日：2005-09-20

申请号：US10714985

申请日：2003-11-17

申请人： William Hong ,  Chia-Che Chung ,  Chi-Wei Chung ,  Wen-Chih Chiou ,  Ying-Ho Chen ,  Syun-Ming Jang

发明人： William Hong ,  Chia-Che Chung ,  Chi-Wei Chung ,  Wen-Chih Chiou ,  Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： B24B1/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/02074 ,  H01L21/02065 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/7684

摘要： An oxide polishing process that is part of a CMP process flow is disclosed. After a copper layer is polished at a first polishing station and a diffusion barrier layer is polished at a second polishing station, a key sequence at a third polish station is the application of a first oxide slurry and a first DI water rinse followed by a second oxide slurry and then a second DI water rinse. As a result, defect counts are reduced from several thousand to less than 100. Another important factor is a low down force that enables more efficient particle removal. The improved oxide polishing process has the same throughput as a single oxide polish and a DI water rinse method and may be implemented in any three slurry copper CMP process flow.

摘要翻译： 公开了作为CMP工艺流程的一部分的氧化物抛光工艺。 在第一抛光站抛光铜层并且在第二抛光站抛光扩散阻挡层之后，在第三抛光工位上的键序列是施加第一氧化物浆料和第一DI水冲洗，然后是第二抛光 氧化物浆液，然后用第二次DI水冲洗。 因此，缺陷计数从几千减少到小于100.另一个重要因素是能够更有效地除去颗粒的低下降力。 改进的氧化物抛光方法具有与单一氧化物抛光剂和DI水漂洗方法相同的生产量，并且可以在任何三种浆料铜CMP工艺流程中实施。