公开(公告)号：US06444371B1

公开(公告)日：2002-09-03

申请号：US09377541

申请日：1999-08-19

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： G03F900

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US5933744A

公开(公告)日：1999-08-03

申请号：US54302

申请日：1998-04-02

申请人： Jeng-Horng Chen ,  Tsu Shih ,  Jui-Yu Chang ,  Chung-Long Chang

发明人： Jeng-Horng Chen ,  Tsu Shih ,  Jui-Yu Chang ,  Chung-Long Chang

IPC分类号： H01L21/3105 ,  H01L23/544 ,  H01L21/465 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L21/31053 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

摘要： A method of alignment for a chemical mechanical polishing includes previously patterning a primary zero alignment mark on a surface of a wafer. A first dielectric layer is deposited on the wafer for isolation. Then, an etching is used to etch the first dielectric layer using a photoresist as a mask. First conductive plugs are formed in the first dielectric layer. Next, a first conductive layer is formed on the surface of the first dielectric layer and on the tungsten plugs. Thus, the first non-zero alignment mark pattern is formed on the surface of the first conductive layer and aligned to the first conductive plugs. Next, a second non-zero alignment mark pattern is thus formed on the surface of a second conductive layer and aligned to the a second conductive plugs. By repeating the aforementioned method, odd non-zero alignment mark patterns will be formed over the first non-zero alignment mark pattern, and even non-zero alignment mark patterns will be formed over the second non-zero alignment mark pattern. Therefore, the present invention save space to put non-zero alignment marks in multilevel interconnection and planarization processes.

摘要翻译： 用于化学机械抛光的对准方法包括预先对晶片表面上的初级零对准标记进行图案化。 第一介电层沉积在晶片上用于隔离。 然后，使用蚀刻来使用光致抗蚀剂作为掩模蚀刻第一介电层。 在第一电介质层中形成第一导电插塞。 接下来，在第一电介质层的表面和钨插塞上形成第一导电层。 因此，第一非零对准标记图案形成在第一导电层的表面上并与第一导电插塞对准。 接下来，在第二导电层的表面上形成第二非零对准标记图案，并与第二导电插塞对准。 通过重复上述方法，将在第一非零对准标记图案上形成奇数非零对准标记图案，并且甚至在第二非零对准标记图案上形成非零对准标记图案。 因此，本发明节省空间，将非零对准标记放置在多层互连和平面化处理中。

公开(公告)号：US5972798A

公开(公告)日：1999-10-26

申请号：US86775

申请日：1998-05-29

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成调制解调器高密度多电平集成电路的所有方法，而不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US06737310B2

公开(公告)日：2004-05-18

申请号：US10236536

申请日：2002-09-06

申请人： Chaochieh Tsai ,  Chung-Long Chang ,  Jui-Yu Chang ,  Shyh-Chyi Wong

发明人： Chaochieh Tsai ,  Chung-Long Chang ,  Jui-Yu Chang ,  Shyh-Chyi Wong

IPC分类号： H01L218238

CPC分类号： H01L21/7681 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating an RF type, MOSFET device, concentrating on reducing performance degrading gate resistance, has been developed. The process features formation of a stacked gate structure, comprised of a metal gate contact structure located directly overlying a portion of an underlying polysilicon gate structure, in a region in which the polysilicon gate structure is located on an active device region of a semiconductor substrate. Subsequent formation of an overlying metal interconnect structure, results in reduced gate resistance due to the direct vertical conductive path from the metal interconnect structure to the polysilicon gate structure, through the metal gate contact structure. A novel process sequence, requiring no photolithographic processing, is used to self-align the metal gate contact structure to the underlying polysilicon gate structure.

摘要翻译： 已经开发了一种用于制造RF型MOSFET器件的方法，其集中在降低性能降低栅极电阻。 该工艺特征是在多晶硅栅极结构位于半导体衬底的有源器件区域上的区域中形成层叠栅极结构，该栅极结构由位于下面的多晶硅栅极结构的一部分直接覆盖的金属栅极接触结构构成。 随后形成上覆的金属互连结构，由于通过金属栅极接触结构从金属互连结构到多晶硅栅极结构的直接垂直导电路径，导致栅极电阻降低。 使用不需要光刻处理的新颖工艺顺序来将金属栅极接触结构自对准到下面的多晶硅栅极结构。

公开(公告)号：US6020249A

公开(公告)日：2000-02-01

申请号：US891088

申请日：1997-07-10

申请人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： G03F9/00 ,  H01L23/544 ,  H01L23/48

CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

公开(公告)号：US5923996A

公开(公告)日：1999-07-13

申请号：US867312

申请日：1997-06-02

申请人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L23/544 ,  H01L21/46 ,  H01L21/301 ,  H01L21/78

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are followed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.

摘要翻译： 公开了一种用于在晶片的外周边形成对准标记的方法，其中它们在化学机械抛光（CMP）工艺期间不会受到很大的损害。 通过蚀刻将对准标记凹入衬底来提供完整的保护。 在同时完成凹槽蚀刻，同时遵循隔离沟以描绘器件区域。 因此，对准标记设置有保护凹槽而没有额外的步骤。 此外，通过在晶片的外周形成对准标记，通过提供用于集成电路的晶片面积的最大使用来提高生产率。

公开(公告)号：US06465897B1

公开(公告)日：2002-10-15

申请号：US09472923

申请日：1999-12-27

申请人： Tsu Shih ,  Jui-Yu Chang

发明人： Tsu Shih ,  Jui-Yu Chang

IPC分类号： H01L2348

CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

摘要翻译： 公开了用于在化学机械抛光（CMP）之后进行光对准的形成对准标记的方法。 首先在硅衬底中形成沟槽，然后在沟槽的底部形成对准标记。 选择沟槽的纵横比非常低以致可以防止CMP焊盘的凹陷进入沟槽以损坏其中的对准标记。 还提供沟槽结构，由此可以保护对准标记免受CMP的研磨作用。 因此，CMP之后的步骤可以不受阻碍地对准标记的存在而不受阻碍地进行。

公开(公告)号：US6080635A

公开(公告)日：2000-06-27

申请号：US67262

申请日：1998-04-27

申请人： Syun-Ming Jang ,  Jui-Yu Chang

发明人： Syun-Ming Jang ,  Jui-Yu Chang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method of preserving alignment marks in integrated circuit substrates using shallow trench isolation after planarization using chemical mechanical polishing. A layer of silicon nitride is formed on the substrate and openings defining alignment trenches and isolation trenches are etched in the silicon nitride layer. Alignment trenches are formed in alignment regions of the substrate and isolation trenches are formed in the active region of the substrate during the same process step using the openings in the silicon nitride layer as a mask. A layer of dielectric is then deposited on the substrate filling the alignment trenches and the isolation trenches. The dielectric is then etched away from the alignment trenches and the substrate is planarized. After a layer of conducting material is deposited on the wafer the alignment trenches are preserved.

摘要翻译： 使用化学机械抛光在平坦化后使用浅沟槽隔离来在集成电路基板中保留对准标记的方法。 在衬底上形成氮化硅层，并且在氮化硅层中蚀刻限定对准沟槽和隔离沟槽的开口。 对准沟槽形成在衬底的对准区域中，并且在使用氮化硅层中的开口作为掩模的相同工艺步骤期间，在衬底的有源区域中形成隔离沟槽。 然后在填充对准沟槽和隔离沟槽的衬底上沉积电介质层。 然后将电介质蚀刻离开对准沟槽，并且将衬底平坦化。 在晶片上沉积一层导电材料之后，保留对准沟槽。

公开(公告)号：US5902707A

公开(公告)日：1999-05-11

申请号：US118035

申请日：1998-07-17

申请人： Tsu-Yu Chu ,  Jui-Yu Chang ,  Kun-Pi Cheng

发明人： Tsu-Yu Chu ,  Jui-Yu Chang ,  Kun-Pi Cheng

IPC分类号： G03F1/00 ,  G03F7/00 ,  G03F9/00

CPC分类号： G03F9/70 ,  G03F1/42 ,  G03F7/0035 ,  Y10S148/102 ,  Y10S438/975

摘要： A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.

摘要翻译： 不需要额外的掩模版的掩模，以及在层间电介质层已被平坦化之后使用掩模来恢复晶片中的对准标记的方法，并且第二层金属已沉积在平坦化的层间电介质上 描述层。 对准标记保护图案和清晰窗口图案被细分，使得它们可以由第一和第二掩模元件形成。 这些掩模元件可以形成在用于对晶片的器件区域进行图案化的掩模版的周边区域中。 掩模元件用于在光致抗蚀剂的第一层中曝光对准标记保护图案，并在第二层光致抗蚀剂中露出清漆窗口图案。

公开(公告)号：US5968687A

公开(公告)日：1999-10-19

申请号：US196601

申请日：1998-11-20

申请人： Jui-Yu Chang ,  Chunshing Chen ,  Syun-Ming Jang ,  Ying-Ho Chen

发明人： Jui-Yu Chang ,  Chunshing Chen ,  Syun-Ming Jang ,  Ying-Ho Chen

IPC分类号： H01L23/544 ,  G03F9/00

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A mask pattern and method are described for the recovery of alignment marks on an integrated circuit wafer without the use of additional masks. The mask pattern and method provide means to recover the alignment marks after forming a metal layer on a planarized inter-level dielectric layer. The pattern which conventional methods have placed on a separate mask is formed in the end regions of a mask used for forming a pattern on the active region of the wafer. In order to fit the pattern in the end regions of the mask the pattern is divided into two parts. When the pattern is used to expose a layer of photoresist two exposure steps are used.

摘要翻译： 描述了用于在集成电路晶片上恢复对准标记的掩模图案和方法，而不使用附加掩模。 掩模图案和方法提供了在平坦化的层间电介质层上形成金属层之后恢复对准标记的装置。 在用于在晶片的有源区上形成图案的掩模的端部区域中形成常规方法已经放置在单独的掩模上的图案。 为了将图案装配在掩模的端部区域中，图案被分为两部分。 当使用图案曝光一层光致抗蚀剂时，使用两个曝光步骤。