公开(公告)号：US20130065331A1

公开(公告)日：2013-03-14

申请号：US13697766

申请日：2011-06-08

申请人： Yasuhiro Koyama ,  Katsuji Kawakami ,  Mutsuo Kawasaki ,  Osamu Miyake ,  Hajime Oda ,  Keiichi Sawai

发明人： Yasuhiro Koyama ,  Katsuji Kawakami ,  Mutsuo Kawasaki ,  Osamu Miyake ,  Hajime Oda ,  Keiichi Sawai

IPC分类号： H01L33/62

CPC分类号： H01L33/62 ,  H01L24/14 ,  H01L24/17 ,  H01L33/38 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/1703 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/15787 ,  H01L2933/0066 ,  H01L2924/00

摘要： The present invention is a method for mounting, on a ceramic substrate (9), an LED chip (1), in which an upper surface of a positive electrode (6) is in a higher position than an upper surface of a negative electrode (5). The method includes the steps of: (i) laminating resist (16) on the negative electrode (5) and the positive electrode (6) and forming openings (16a and 16b) in the resist (16); (ii) forming bumps (11 and 12) in the respective openings (16a and 16b); (iii) removing the resist (16); and (iv) bonding bumps (11 and 12) to the ceramic substrate (9). A cross-sectional area of the opening (16a) is larger than a cross-sectional area of the opening (16b).

摘要翻译： 本发明是一种在陶瓷基板（9）上安装LED芯片（1）的方法，其中正极（6）的上表面位于比负极的上表面更高的位置（ 5）。 该方法包括以下步骤：（i）在抗蚀剂（16）上的负极（5）和正电极（6）上层压抗蚀剂（16）和形成开口（16a和16b）; （ii）在各个开口（16a和16b）中形成凸块（11和12）; （iii）除去抗蚀剂（16）; 和（iv）将凸块（11和12）接合到陶瓷基板（9）上。 开口（16a）的横截面面积大于开口（16b）的横截面面积。

公开(公告)号：US07259621B2

公开(公告)日：2007-08-21

申请号：US11045262

申请日：2005-01-31

申请人： Shigeo Kusunoki ,  Katsuji Kawakami

发明人： Shigeo Kusunoki ,  Katsuji Kawakami

IPC分类号： H03F1/26

CPC分类号： H03F1/3276

摘要： One divided signal divided into two by a dividing circuit is inputted to a gate of a source grounded FET through a first matching circuit. In a drain of the FET, a second harmonic having a phase and an amplitude in accordance with an impedance of the first matching circuit is generated and extracted in a band pass filter and then the amplitude is adjusted in an attenuation circuit to input to an addition circuit through a second matching circuit. In the addition circuit, the output of the second matching circuit is added to another divided signal of the dividing circuit and inputted to a power amplifier. The impedance in the first matching circuit affecting the phase of the second harmonic generated from the FET is set so that a distortion component generated in the power amplifier is compensated for by the second harmonic inputted in the addition circuit.

摘要翻译： 通过分频电路将二分频信号通过第一匹配电路输入到源极接地FET的栅极。 在FET的漏极中，在带通滤波器中产生并提取具有根据第一匹配电路的阻抗的相位和幅度的二次谐波，然后在衰减电路中调整振幅以输入到加法 电路通过第二匹配电路。 在加法电路中，将第二匹配电路的输出添加到除法电路的另一分频信号并输入功率放大器。 影响从FET产生的二次谐波的相位的第一匹配电路中的阻抗被设定为使得在功率放大器中产生的失真分量由输入到加法电路中的二次谐波补偿。

公开(公告)号：US09048407B2

公开(公告)日：2015-06-02

申请号：US13697766

申请日：2011-06-08

申请人： Yasuhiro Koyama ,  Katsuji Kawakami ,  Mutsuo Kawasaki ,  Osamu Miyake ,  Hajime Oda ,  Keiichi Sawai

发明人： Yasuhiro Koyama ,  Katsuji Kawakami ,  Mutsuo Kawasaki ,  Osamu Miyake ,  Hajime Oda ,  Keiichi Sawai

IPC分类号： H01L21/00 ,  H01L33/62 ,  H01L23/00 ,  H01L33/38

CPC分类号： H01L33/62 ,  H01L24/14 ,  H01L24/17 ,  H01L33/38 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/1703 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/15787 ,  H01L2933/0066 ,  H01L2924/00

摘要： The present invention is a method for mounting, on a ceramic substrate (9), an LED chip (1), in which an upper surface of a positive electrode (6) is in a higher position than an upper surface of a negative electrode (5). The method includes the steps of: (i) laminating resist (16) on the negative electrode (5) and the positive electrode (6) and forming openings (16a and 16b) in the resist (16); (ii) forming bumps (11 and 12) in the respective openings (16a and 16b); (iii) removing the resist (16); and (iv) bonding bumps (11 and 12) to the ceramic substrate (9). A cross-sectional area of the opening (16a) is larger than a cross-sectional area of the opening (16b).

摘要翻译： 本发明是一种在陶瓷基板（9）上安装LED芯片（1）的方法，其中正极（6）的上表面位于比负极的上表面更高的位置（ 5）。 该方法包括以下步骤：（i）在抗蚀剂（16）上的负极（5）和正电极（6）上层压抗蚀剂（16）和形成开口（16a和16b）; （ii）在各个开口（16a和16b）中形成凸块（11和12）; （iii）除去抗蚀剂（16）; 和（iv）将凸块（11和12）接合到陶瓷基板（9）上。 开口（16a）的横截面面积大于开口（16b）的横截面面积。

公开(公告)号：US20090149014A1

公开(公告)日：2009-06-11

申请号：US12098610

申请日：2008-04-07

申请人： Norimitsu NIE ,  Masahiro HORIO ,  Keiichi SAWAI ,  Yuji WATANABE ,  Yasuhiro KOYAMA ,  Katsuji KAWAKAMI

发明人： Norimitsu NIE ,  Masahiro HORIO ,  Keiichi SAWAI ,  Yuji WATANABE ,  Yasuhiro KOYAMA ,  Katsuji KAWAKAMI

IPC分类号： H01L21/60

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00014

摘要： At step S101, a TiW film is formed by a sputtering method so as to cover a surface protection film and pad electrodes formed on a surface of a semiconductor element. Subsequently, an Au film is formed on the TiW film. At step S103, Au bumps are formed on the Au film using the Au film as a plating electrode. At step S105, unnecessary parts of the Au film are removed. At step S106, unnecessary parts of the TiW film are removed. At step S107, iodine left in areas where the unnecessary parts of the TiW film have been removed, is removed.

摘要翻译： 在步骤S101中，通过溅射法形成TiW膜，以覆盖形成在半导体元件的表面上的表面保护膜和焊盘电极。 随后，在TiW膜上形成Au膜。 在步骤S103中，使用Au膜作为电镀电极，在Au膜上形成Au凸块。 在步骤S105，除去Au膜的不必要部分。 在步骤S106，除去TiW膜的不必要部分。 在步骤S107中，除去已经去除了TiW膜的不需要部分的区域中的碘。

公开(公告)号：US20050212595A1

公开(公告)日：2005-09-29

申请号：US11045262

申请日：2005-01-31

申请人： Shigeo Kusunoki ,  Katsuji Kawakami

发明人： Shigeo Kusunoki ,  Katsuji Kawakami

IPC分类号： H03F1/32 ,  H03F3/24 ,  H04B1/04 ,  H03F1/26

CPC分类号： H03F1/3276

摘要： One divided signal divided into two by a dividing circuit is inputted to a gate of a source grounded FET through a first matching circuit. In a drain of the FET, a second harmonic having a phase and an amplitude in accordance with an impedance of the first matching circuit is generated and extracted in a band pass filter and then the amplitude is adjusted in an attenuation circuit to input to an addition circuit through a second matching circuit. In the addition circuit, the output of the second matching circuit is added to another divided signal of the dividing circuit and inputted to a power amplifier. The impedance in the first matching circuit affecting the phase of the second harmonic generated from the FET is set so that a distortion component generated in the power amplifier is compensated for by the second harmonic inputted in the addition circuit.

摘要翻译： 通过分频电路将二分频信号通过第一匹配电路输入到源极接地FET的栅极。 在FET的漏极中，在带通滤波器中产生并提取具有根据第一匹配电路的阻抗的相位和幅度的二次谐波，然后在衰减电路中调整振幅以输入到加法 电路通过第二匹配电路。 在加法电路中，将第二匹配电路的输出添加到除法电路的另一分频信号并输入功率放大器。 影响从FET产生的二次谐波的相位的第一匹配电路中的阻抗被设定为使得在功率放大器中产生的失真分量由输入到加法电路中的二次谐波补偿。