公开(公告)号：US5223442A

公开(公告)日：1993-06-29

申请号：US911293

申请日：1992-07-09

申请人： Mitsuhiko Kitagawa ,  Yoshio Yokota ,  Kazuo Watanuki ,  Yoshinari Uetake ,  Kazunobu Nishitani ,  Tsuneo Ogura

发明人： Mitsuhiko Kitagawa ,  Yoshio Yokota ,  Kazuo Watanuki ,  Yoshinari Uetake ,  Kazunobu Nishitani ,  Tsuneo Ogura

IPC分类号： H01L21/332 ,  H01L23/051 ,  H01L29/08 ,  H01L29/36 ,  H01L29/744 ,  H01L29/868

CPC分类号： H01L29/66363 ,  H01L23/051 ,  H01L24/01 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/66136 ,  H01L29/744 ,  H01L29/8613 ,  H01L29/868 ,  H01L29/0661 ,  H01L2924/1301 ,  H01L2924/351

摘要： Phosphorus is doped into one of the major surfaces of an n-type silicon semiconductor substrate, and boron is doped into the other major surface. Thereafter, the structure is diffused into the surface regions of the substrate at a high temperature and for a long time, so that an n-buffer layer is formed in the first major surface, and a p-base layer is formed in the second major surface. Impurity of n-type is diffused into the p-base layer, to form an n-emitter layer. Impurity of p-type is diffused into the n-buffer layer, to selectively form p-emitter layer. Further, n-type impurity is diffused into the n-buffer layer, to form n-type anode short layer.

摘要翻译： 磷被掺杂到n型硅半导体衬底的主表面之一中，并且硼掺杂到另一个主表面中。 此后，该结​​构在高温下长时间扩散到基板的表面区域，使得在第一主表面形成n缓冲层，在第二主表面形成p基层 表面。 n型的杂质扩散到p基层中，形成n-发射极层。 p型的杂质扩散到n缓冲层中，以选择性地形成p-发射极层。 此外，n型杂质扩散到n缓冲层中，形成n型阳极短层。

公开(公告)号：US5156981A

公开(公告)日：1992-10-20

申请号：US334257

申请日：1989-04-06

申请人： Mitsuhiko Kitagawa ,  Yoshio Yokota ,  Kazuo Watanuki ,  Yoshinari Uetake ,  Kazunobu Nishitani ,  Tsuneo Ogura

发明人： Mitsuhiko Kitagawa ,  Yoshio Yokota ,  Kazuo Watanuki ,  Yoshinari Uetake ,  Kazunobu Nishitani ,  Tsuneo Ogura

IPC分类号： H01L29/861 ,  H01L21/332 ,  H01L23/051 ,  H01L29/08 ,  H01L29/36 ,  H01L29/74 ,  H01L29/744 ,  H01L29/868

CPC分类号： H01L29/66363 ,  H01L23/051 ,  H01L24/01 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/744 ,  H01L29/868 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/1301 ,  H01L2924/351

摘要： Phosphorus is doped into one of the major surfaces of an n-type silicon semiconductor substrate, and boron is doped into the other major surface. Thereafter, the structure is diffused into the surface regions of the substrate at a high temperature and for a long time, so that an n-buffer layer is formed in the first major surface, and a p-base layer is formed in the second major surface. Impurity of n-type is diffused into the p-base layer, to form an n-emitter layer. Impurity of p-type is diffused into the n-buffer layer, to selectively form p-emitter layer. Further, n-type impurity is diffused into the n-buffer layer, to form n-type anode short layer.

公开(公告)号：US5210601A

公开(公告)日：1993-05-11

申请号：US817952

申请日：1992-01-06

申请人： Mitsuhiko Kitagawa ,  Yoshio Yokota ,  Kazuo Watanuki, deceased

发明人： Mitsuhiko Kitagawa ,  Yoshio Yokota ,  Kazuo Watanuki, deceased

IPC分类号： H01L23/48

CPC分类号： H01L24/72 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055

摘要： According to this invention, a compression contacted semiconductor device is characterized by including a semiconductor pellet having main electrodes formed a first major surface of one surface side and a second major surface of another surface side, and electrode posts arranged on at least one major surface of the semiconductor pellet through an electrode member to sandwich the semiconductor pellet to compress the electrodes of the first and second major surfaces, wherein a crystal defect density is distributed within a surface of the semiconductor pellet so that a carrier lifetime of at least heat generating portions in the surface of the semiconductor pellet which do not sufficiently conduct heat to the electrode posts is shorter than a carrier lifetime of major heat generating portions which sufficiently conduct heat to the electrode posts. For this reason, current in the heat generating portions which do not sufficiently conduct heat to the electrode members is decreased. Therefore, the amount of heat generation is reduced, and the break-down voltage of a semiconductor element is increased.

摘要翻译： 根据本发明，压电接触半导体器件的特征在于包括：半导体芯片，其具有形成有一个表面侧的第一主表面和另一个表面侧的第二主表面的主电极，以及设置在至少一个主表面上的电极柱 所述半导体颗粒通过电极构件夹持半导体颗粒以压缩第一和第二主表面的电极，其中晶体缺陷密度分布在半导体芯片的表面内，使得至少发热部分的载流子寿命 不足够地向电极柱传导热量的半导体芯片的表面比向电极柱充分传导热量的主要发热部分的载流子寿命短。 因此，不能充分地向电极部件传导热量的发热部的电流降低。 因此，发热量减少，半导体元件的击穿电压升高。

公开(公告)号：US4996586A

公开(公告)日：1991-02-26

申请号：US422900

申请日：1989-10-17

申请人： Hideo Matsuda ,  Takashi Fujiwara ,  Yoshio Yokota ,  Mitsuhiko Kitagawa ,  Masami Iwasaki ,  Kazuo Watanuki

发明人： Hideo Matsuda ,  Takashi Fujiwara ,  Yoshio Yokota ,  Mitsuhiko Kitagawa ,  Masami Iwasaki ,  Kazuo Watanuki

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/52 ,  H01L23/051 ,  H01L23/48 ,  H01L23/482 ,  H01L29/74 ,  H01L29/744

CPC分类号： H01L23/051 ,  H01L23/4824 ,  H01L24/72 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/13033 ,  H01L2924/351

摘要： A crimp-type semiconductor device having a non-alloy structure according to this invention has a silicon pellet including a plurality of cathode electrodes and a plurality of gate electrodes arranged to be alternately staggered with the cathode electrodes at the cathode side, and an anode electrode at the anode side. The cathode electrodes are crimped by a cathode electrode post via an electrode member constituted by a thin soft-metal plate and a hard metal plate. The anode electrode is crimped by an anode electrode post via an electrode member. Opposing surfaces of the electrodes, the electrode members, and the electrode posts are not bonded to but crimped in contact with each other. The electrode members are formed to cover the entire surfaces of the cathode electrode and the anode electrode, respectively, and the entire surface of the cathode electrode post and the anode electrode post, respectively. The electrode members and the electrode posts are positioned with respect to each other by positioning guides, respectively.

公开(公告)号：US5028974A

公开(公告)日：1991-07-02

申请号：US474238

申请日：1990-02-05

申请人： Mituhiko Kitagawa ,  Tsuneo Ogura ,  Hiromichi Ohashi ,  Yoshinari Uetake ,  Yoshio Yokota ,  Kazuo Watanuki

发明人： Mituhiko Kitagawa ,  Tsuneo Ogura ,  Hiromichi Ohashi ,  Yoshinari Uetake ,  Yoshio Yokota ,  Kazuo Watanuki

IPC分类号： H01L29/08 ,  H01L29/74 ,  H01L29/744 ,  H01L29/745

CPC分类号： H01L29/744 ,  H01L29/0834 ,  H01L29/7428 ,  H01L29/7455

摘要： A semiconductor switching device includes a high resistance first base layer of n-type formed on a first emitter layer of p-type through a low resistance buffer layer of n.sup.+ -type, second base layer of p-type formed on the first base layer, second emitter layers of n.sup.+ -type separately formed on the second base layer, anode and cathode main electrodes formed in contact with the first and second emitter layers, and a gate electrode formed in contact with the second base layer. Part of the low resistance buffer layer is exposed to the surface of the first emitter layer and is made contact with the anode main electrode to constitute a shorting portion. The width of the shorting portion is set smaller than one tenth of that of the second emitter layer in a longitudinal direction.

摘要翻译： 一种半导体开关器件包括通过形成在第一基极层上的n +型第二基极层p型的低电阻缓冲层形成在p型第一发射极层上的n型高电阻第一基极层， 分别形成在第二基极层上的n +型第二发射极层，与第一和第二发射极层形成的阳极和阴极主电极以及与第二基极层接触形成的栅电极。 低电阻缓冲层的一部分暴露于第一发射极层的表面，并与阳极主电极接触以构成短路部分。 短路部的宽度设定为小于第二发射极层的长度方向的宽度的十分之一。