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公开(公告)号：US08527175B2
公开(公告)日：2013-09-03
申请号：US13156621
申请日：2011-06-09
CPC分类号： B60T7/122 , B60T2201/06 , B60W10/06 , B60W10/188 , B60W30/18027 , B60W30/18118 , B60W2510/0657 , B60W2510/1005 , B60W2510/105 , B60W2510/182 , B60W2550/142 , Y10T477/6422
摘要： A braking/driving control apparatus for a vehicle includes a basic control unit which calculates and outputs a target axle torque based on a target acceleration and a driving resistance of the vehicle and which determines an axle torque for a power train of the vehicle and an axle torque for a braking apparatus of the vehicle based on the calculated target axle torque, a sliding-down prediction determining unit which determines whether there is a possibility that the vehicle slides down rearwards on an uphill road, and a sliding-down preventing process executing unit which performs a process for reducing a possibility that the vehicle slides down, based on a determination result of the sliding-down prediction determining unit. After the sliding-down prediction determining unit determines that there is the possibility, the sliding-down preventing process executing unit controls the basic control unit to calculate and output the target axle torque so as to reach an axle torque which is obtained by reducing a predetermined positive amount form an estimated value of an axle torque necessary for the vehicle to achieve the target acceleration against the driving resistance.
摘要翻译： 一种用于车辆的制动/驱动控制装置，包括基本控制单元，该基本控制单元基于车辆的目标加速度和驾驶阻力来计算并输出目标车轴扭矩，并且确定车辆和车轴的动力传动系的车轴扭矩 基于计算出的目标车轴转矩的用于车辆的制动装置的转矩，确定车辆是否存在在上坡路上向后滑动的可能性的滑落预测确定单元，以及下滑防止处理执行单元 其基于滑下预测判定单元的判定结果，进行用于降低车辆下滑的可能性的处理。 在滑下预测确定单元确定存在可能性之后，下滑防止处理执行单元控制基本控制单元以计算和输出目标车轴扭矩，以达到通过减少预定的 正值形成车辆相对于驱动阻力实现目标加速度所需的车轴转矩的估计值。
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公开(公告)号：US07454589B2
公开(公告)日：2008-11-18
申请号：US11102656
申请日：2005-04-11
IPC分类号： G06F1/12
CPC分类号： G06F13/405
摘要： There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.
摘要翻译： 提供缓冲电路缓冲同步电路和异步电路之间的数据及其控制方法。 还提供了一种控制同步存储器电路和异步电路之间的数据传输的接口电路及其控制方法，其用于缓冲电路及其控制方法。 介于图像处理系统和主系统之间的数据缓冲电路包括单端口RAM，控制信号产生部分，后续周期地址生成部分和第一选择器。 当对单端口RAM的访问是写访问时，第一选择器有选择地将当前周期地址输出到单端口RAM的地址，并且当第一选择器输入后续周期地址到单端口RAM的地址时 访问单端口RAM是一种读取访问。
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公开(公告)号：US07408831B2
公开(公告)日：2008-08-05
申请号：US11652590
申请日：2007-01-12
IPC分类号： G11C5/14
CPC分类号： G11C5/025 , G11C5/14 , G11C5/143 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084
摘要： A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.
摘要翻译： 一种用于容易地改变I / O电路的工作电压的半导体器件。 I / O电路包括用第一高电位电源操作的第一I / O单元和与第二高电位电源一起工作的第二I / O单元。 I / O电路包括用于根据电压选择信号选择性地激活第一和第二I / O单元的控制电路。 在I / O电路中，产生具有根据所选I / O单元的工作电压的电压的信号。
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公开(公告)号：US20060129720A1
公开(公告)日：2006-06-15
申请号：US11102656
申请日：2005-04-11
IPC分类号： G06F3/06
CPC分类号： G06F13/405
摘要： There are provided a buffer circuit buffers data between a synchronous circuit and an asynchronous circuit, and a control method therefor. There are also provided an interface circuit that controls data transfer between a synchronous memory circuit and the asynchronous circuit, and a control method therefor, which are used in the buffer circuit and the control method therefor. A data buffer circuit that is interposed between an image processing system and a main system includes a one-port RAM, a control signal generating section, an subsequent cycle address generating section, and a first selector. The first selector selectively outputs the present cycle address to an address of the one-port RAM when an access to the one-port RAM is a write access, and selectively outputs the subsequent cycle address to the address of the one-port RAM when the access to the one-port RAM is a read access.
摘要翻译： 提供缓冲电路缓冲同步电路和异步电路之间的数据及其控制方法。 还提供了一种控制同步存储器电路和异步电路之间的数据传送的接口电路及其控制方法，其用于缓冲电路及其控制方法。 介于图像处理系统和主系统之间的数据缓冲电路包括单端口RAM，控制信号产生部分，后续周期地址生成部分和第一选择器。 当对单端口RAM的访问是写访问时，第一选择器有选择地将当前周期地址输出到单端口RAM的地址，并且当第一选择器输入后续周期地址到单端口RAM的地址时 访问单端口RAM是一种读取访问。
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公开(公告)号：US06895496B1
公开(公告)日：2005-05-17
申请号：US09266869
申请日：1999-03-12
CPC分类号： G06F9/3804 , G06F9/30058
摘要： A microcontroller, connected to a memory which stores instructions and data, includes an instruction execution unit for reading instructions and data from the memory and processing the read instructions and a prefetch circuit unit that receives the instructions and data read from the memory and detects pseudo instructions included in the instructions and data. A pseudo instruction precedes a branch instruction and indicates the existence of the branch instruction and the branch to address. The prefetch circuit unit includes a prefetch buffer connected between the instruction execution unit and the memory for temporarily storing instructions and data being transferred from the memory to the instruction execution unit and a pseudo instruction buffer for temporarily storing instructions and data located at the address of the branch instruction which follows the pseudo instruction. Then, if the branch is taken, the branch to instructions have been prefetched and are immediately available to the instruction execution unit by way of the pseudo instruction buffer.
摘要翻译： 连接到存储指令和数据的存储器的微控制器包括用于从存储器读取指令和数据并处理读取指令的指令执行单元和接收从存储器读取的指令和数据并检测伪指令的预取电路单元 包含在说明书和数据中。 伪指令先于分支指令，并指示分支指令的存在和分支到地址。 预取电路单元包括连接在指令执行单元和存储器之间的预取缓冲器，用于临时存储从存储器传送到指令执行单元的指令和数据;以及伪指令缓冲器，用于临时存储位于指令执行单元的地址处的指令和数据 遵循伪指令的分支指令。 然后，如果分支被采取，则指令的分支已被预取，并且可以通过伪指令缓冲器立即可用于指令执行单元。
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公开(公告)号：US06502179B2
公开(公告)日：2002-12-31
申请号：US09768363
申请日：2001-01-25
申请人： Teruyoshi Kondo , Masayuki Takeshige , Sumitaka Hibino , Hayato Isobe , Yukisato Miyazaki , Kunihiro Ohara , Kazuya Taniguchi , Hiroshi Naritomi
发明人： Teruyoshi Kondo , Masayuki Takeshige , Sumitaka Hibino , Hayato Isobe , Yukisato Miyazaki , Kunihiro Ohara , Kazuya Taniguchi , Hiroshi Naritomi
IPC分类号： G06F1204
CPC分类号： G06F9/3816 , G06F9/30149 , G06F9/32 , G06F12/04
摘要： A processor for performing calculations based on an instruction code, the number of bits of which is not an integer multiple of a byte. The instruction code is divided into higher order bits and lower order bits. The number of the lower order bits is an integer multiple of one byte. A memory stores the lower order bits in a lower order bit storage section and the higher order bits in a higher order bit storage section. The lower order bits and the corresponding higher order bits are read from the memory in the same cycle when generating the instruction code.
摘要翻译： 一种用于基于指令代码执行计算的处理器，其位的数量不是字节的整数倍。 指令码分为较高位和较低位。 低位数的数量是一个字节的整数倍。 存储器将低位位存储在较低阶位存储部分中，而较高位位存储在较高位存储部分中。 当产生指令代码时，在相同周期中从存储器读取低位和低位。
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公开(公告)号：US20070276964A1
公开(公告)日：2007-11-29
申请号：US11701384
申请日：2007-02-02
申请人： Kazuya Taniguchi , Osamu Matsuura , Kazuo Ohno
发明人： Kazuya Taniguchi , Osamu Matsuura , Kazuo Ohno
IPC分类号： G06F3/00
CPC分类号： H03K19/00315 , H03K19/017509
摘要： The present invention provides an input/output device capable of bringing a per-unit input/output circuit into a simple configuration without impairing reliability even when logic levels opposite in polarity are outputted between input/output devices made conductive to the outside. The input/output device is equipped with one reference port Pk selected from a port group which inputs and outputs signals, target ports Pt selected from other than the reference port of the port group, and a conduction detector which detects that conduction is made between input/output terminals for the reference port Pk and the target ports Pt.
摘要翻译： 本发明提供了一种能够将单位输入/输出电路简单配置而不损害可靠性的输入/输出装置，即使在与外部导通的输入/输出装置之间输出极性相反的逻辑电平时也是如此。 输入/输出装置配备有从端口组中选择的一个参考端口Pk，其输入和输出信号，从端口组的参考端口以外选择的目标端口Pt以及检测在输入之间进行导通的导电检测器 /参考端口Pk和目标端口Pt的输出端子。
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公开(公告)号：US07283416B2
公开(公告)日：2007-10-16
申请号：US11652589
申请日：2007-01-12
IPC分类号： G11C5/14
CPC分类号： G11C5/025 , G11C5/14 , G11C5/143 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084
摘要： A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.
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公开(公告)号：US20060039206A1
公开(公告)日：2006-02-23
申请号：US10997891
申请日：2004-11-29
CPC分类号： G11C5/025 , G11C5/14 , G11C5/143 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084
摘要： A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. The I/O circuit includes a control circuit for selectively activating the first and second I/O cells according to a voltage selection signal. In the I/O circuit, a signal having a voltage according to an operating voltage of the selected I/O cell is generated.
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公开(公告)号：US20050213380A1
公开(公告)日：2005-09-29
申请号：US10509937
申请日：2003-04-04
申请人： Kazuya Taniguchi , Naoya Iguchi , Yasuhito Soma , Hisato Hayakawa
发明人： Kazuya Taniguchi , Naoya Iguchi , Yasuhito Soma , Hisato Hayakawa
CPC分类号： G06F1/3209 , G06F1/263 , G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： In a multiple power source semiconductor integrated circuit that is manufactured using a process which generates a large leakage current, supply of power to a function block that is not being used is stopped to reduce unnecessary power consumption. A multiple power source semiconductor integrated circuit (1) includes first to fourth function blocks (11) to (14) that are supplied with power from first to fourth power supply circuits (3) to (6), respectively, and a power supply control circuit (40) that controls supply of power by the first to fourth power supply circuits (3) to (6) under the control of a microcomputer as the first function block (11). The power supply control circuit (40) halts the supply of power to the first to fourth function blocks (11) to (14) when receiving prescribed data from the first function block (11), and restarts the supply of power when receiving a first or second interrupt signal (55) or (56) from outside.
摘要翻译： 在使用产生大泄漏电流的处理制造的多电源半导体集成电路中，停止向未使用的功能块的电力供给，以减少不必要的功耗。 多电源半导体集成电路（1）包括从第一至第四电源电路（3）至（6）分别供电的第一功能块（11）至第四功能块（14），以及电源控制 电路（40），其在微型计算机的控制下控制第一至第四电源电路（3）至（6）的电力供应作为第一功能块（11）。 当从第一功能块（11）接收到规定数据时，电源控制电路（40）停止向第一至第四功能块（11）至（14）的电力供应，并且当接收到第一功能块 或第二中断信号（55）或（56）。
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