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公开(公告)号：US07433426B2
公开(公告)日：2008-10-07
申请号：US10831095
申请日：2004-04-23
CPC分类号： H04L25/063 , H03K5/082 , H03K5/1252
摘要： An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.
摘要翻译： 自适应迟滞接收器处理高速数字信号。 差分接收器电路将高速数字信号与参考电压进行比较以产生输出信号。 寄存器电路根据时钟信号锁存输出信号以产生控制信号。 参考电压发生器响应于输出信号和控制信号从限定深滞后电平和浅滞后电平的多个电压产生参考电压。
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公开(公告)号：US06778111B1
公开(公告)日：2004-08-17
申请号：US10653341
申请日：2003-09-02
申请人： Zhubiao Zhu , Kenneth Koch, II
发明人： Zhubiao Zhu , Kenneth Koch, II
IPC分类号： H03M100
CPC分类号： H03K5/088 , H03K3/02337 , H03K5/1252 , H04L25/08
摘要： A system and method provide deglitch filtering. The system has a voltage-based deglitching filter and timing-based deglitching filter. The voltage-based deglitching filter connects with the timing-based deglitch filter, such that the output of the voltage-based deglitch filter connects to the input of the timing-based deglitch filter. The voltage-based deglitch filter is in feedback with the timing based deglitching filter.
摘要翻译： 系统和方法提供deglitch滤波。 该系统具有基于电压的去角度滤波器和基于定时的去角度滤波器。 基于电压的去角滤波器与基于定时的去隙滤波器连接，使得基于电压的去隔离滤波器的输出连接到基于时序的去离子滤波器的输入。 基于电压的deglitch滤波器与基于定时的去角度滤波器反馈。
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3.发明授权Method and system for performing sampling on the fly using minimum cycle delay synchronization 有权使用最小循环延迟同步在飞行中执行采样的方法和系统公开(公告)号：US06734709B1
公开(公告)日：2004-05-11
申请号：US10383127
申请日：2003-03-06
IPC分类号： H03K3017
摘要： A method and system for sampling on the fly one or more integrated circuit nodes coupled to one or more bus domain clocks of an integrated circuit using minimal clock cycle delay synchronization. Sample on the fly circuitry, set-reset circuitry and metastable rejection circuitry are used to provide a sufficient pulse width for sampling on the fly the one or more nodes when the one or more bus domain clocks require asynchronous operation. The sample on the fly circuitry is also operable to synchronously sample on the fly the one or more nodes.
摘要翻译： 一种用于使用最小时钟周期延迟同步在一个或多个集成电路节点上采集集成电路的一个或多个总线域时钟的方法和系统。 当一个或多个总线域时钟需要异步操作时，在飞行电路，设置复位电路和亚稳态抑制电路上的采样用于提供足够的脉冲宽度用于在一个或多个节点上飞行时进行采样。 飞行电路上的采样也可用于在一个或多个节点上同时采样。
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公开(公告)号：US20150155686A1
公开(公告)日：2015-06-04
申请号：US14379554
申请日：2012-04-25
申请人： Daniel A. Berkram , Dacheng Zhou , Zhubiao Zhu
发明人： Daniel A. Berkram , Dacheng Zhou , Zhubiao Zhu
CPC分类号： H01S5/042 , H01S5/0617 , H01S5/06808 , H01S5/183
摘要： Methods, systems, and devices are provided for operating a vertical-cavity surface-emitting laser. Operating a vertical-cavity surface-emitting laser can include determining an output voltage of a vertical-cavity surface-emitting laser driver, determining a relationship between the output voltage and a reference voltage, and adjusting an output current of the vertical-cavity surface-emitting laser driver based, at least in part, on the determined relationship.
摘要翻译： 提供了用于操作垂直腔表面发射激光器的方法，系统和装置。 操作垂直腔表面发射激光器可以包括确定垂直腔表面发射激光器驱动器的输出电压，确定输出电压和参考电压之间的关系，以及调整垂直腔表面发射激光器的输出电流。 至少部分地基于确定的关系发射激光驱动器。
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公开(公告)号：US20150054555A1
公开(公告)日：2015-02-26
申请号：US14387618
申请日：2012-04-26
申请人： Daniel A. Berkram , Zhubiao Zhu
发明人： Daniel A. Berkram , Zhubiao Zhu
CPC分类号： H03L7/091 , H03K5/135 , H03L7/0812 , H03L7/093 , H03L7/1075 , H03L2207/04
摘要： Apparatuses and methods for a self-biased delay looked loop with delay linearization are provided. One example delay locked loop (DU) circuit (100, 200) can include a digital-to-analog converter (DAC) (104, 204, 304) and a bias generator (188, 208) communicatively coupled to an output of the DAC (106, 206, 306). The bias generator (108, 206) is configured to provide a clock signal and a bias signal. A delay control circuit (DCC) (109, 209) is communicatively coupled to the bias generator (108, 208). The DCC (109, 209) is configured to provide a delayed clock signal based on the clock signal and the bias signal. A DAC bias circuit (122, 222, 422) is communicatively coupled to the DAC (106, 206, 306) and configured to provide a feedback signal to the DAC (104, 204, 304) based on the bias signal. The DAC bias circuit (122, 222, 422) configured to adjust the feedback signal to cause the delayed clock signal at the output of the DAC (106, 206, 306) to be non-linear to counteract non-linear delay characteristics of the DCC (109, 209).
摘要翻译： 提供了具有延迟线性化的自偏置延迟看法循环的装置和方法。 一个示例的延迟锁定环路（DU）电路（100,200）可以包括数模转换器（DAC）（104,204,304）和通信地耦合到DAC的输出的偏置发生器（188,208） （106,206,306）。 偏置发生器（108,206）被配置为提供时钟信号和偏置信号。 延迟控制电路（DCC）（109,209）通信地耦合到偏置发生器（108,208）。 DCC（109,209）被配置为基于时钟信号和偏置信号提供延迟的时钟信号。 DAC偏置电路（122,222,422）通信地耦合到DAC（106,206,306），并且被配置为基于偏置信号向DAC（104,204,304）提供反馈信号。 所述DAC偏置电路（122,222,422）被配置为调整所述反馈信号以使所述DAC（106,206,306）的输出处的所述经延迟的时钟信号是非线性的，以抵消所述DAC的非线性延迟特性 DCC（109,209）。
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公开(公告)号：US09166367B2
公开(公告)日：2015-10-20
申请号：US14386183
申请日：2012-04-25
申请人： Zhubiao Zhu , Dacheng Zhou , Daniel A. Berkram
发明人： Zhubiao Zhu , Dacheng Zhou , Daniel A. Berkram
IPC分类号： H01S3/13 , H01S5/06 , H01S5/068 , H01S5/0683 , H01S5/183 , H01S3/131 , H04B10/564 , H01S5/42
CPC分类号： H01S5/06 , H01S3/13 , H01S3/1306 , H01S3/131 , H01S5/068 , H01S5/06832 , H01S5/183 , H01S5/423 , H04B10/564
摘要： Methods, systems, and computer-readable media are provided for operating a vertical-cavity surface-emitting laser. Operating a vertical-cavity surface-emitting laser can include sending a signal to a driver to decrease an optical power of a vertical cavity surface emitting laser transmitter, and sending a signal to the driver associated with increasing the optical power by a particular amount in response to determining that the optical power is insufficient for reception by a receiver.
摘要翻译： 提供了用于操作垂直腔表面发射激光器的方法，系统和计算机可读介质。 操作垂直腔表面发射激光器可以包括向驾驶员发送信号以降低垂直腔表面发射激光发射器的光功率，并且向响应于发射信号的光功率增加特定量发送信号到驱动器 以确定光功率不足以用于接收机的接收。
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公开(公告)号：US20150110142A1
公开(公告)日：2015-04-23
申请号：US14386183
申请日：2012-04-25
申请人： Zhubiao Zhu , Dacheng Zhou , Daniel A. Berkram
发明人： Zhubiao Zhu , Dacheng Zhou , Daniel A. Berkram
CPC分类号： H01S5/06 , H01S3/13 , H01S3/1306 , H01S3/131 , H01S5/068 , H01S5/06832 , H01S5/183 , H01S5/423 , H04B10/564
摘要： Methods, systems, and computer-readable mediah are provided for operating a vertical-cavity surface-emitting laser. Operating a vertical-cavity surface-emitting laser can include sending a signal to a driver to decrease an optical power of a vertical cavity surface emitting laser transmitter, and sending a signal to the driver associated with increasing the optical power by a particular amount in response to determining that the optical power is insufficient for reception by a receiver.
摘要翻译： 提供了用于操作垂直腔表面发射激光器的方法，系统和计算机可读介质。 操作垂直腔表面发射激光器可以包括向驾驶员发送信号以降低垂直腔表面发射激光发射器的光功率，并且向响应于发射信号的光功率增加特定量发送信号到驱动器 以确定光功率不足以用于接收机的接收。
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公开(公告)号：US20150050029A1
公开(公告)日：2015-02-19
申请号：US14387264
申请日：2012-04-25
申请人： Dacheng Zhou , Daniel A. Berkram , Zhubiao Zhu
发明人： Dacheng Zhou , Daniel A. Berkram , Zhubiao Zhu
IPC分类号： H04B10/564 , G06F1/32 , H04B10/27
CPC分类号： H04B10/564 , G06F1/3296 , H04B10/27
摘要： Methods, systems, and computer-readable media are provided for operating a vertical cavity surface-emitting laser. Operating a vertical-cavity surface-emitting laser can include receiving an optical signal from a transmitter, converting the optical signal to a waveform, generating a read capture window based on the waveform, sampling data at a first position in the read capture window, sampling data at a second position in the read capture window, and sending a signal to the transmitter to increase a power level of the optical signal in response to a difference between the sampled data at the first position and the sampled data at the second position exceeding a threshold.
摘要翻译： 提供了用于操作垂直腔表面发射激光器的方法，系统和计算机可读介质。 操作垂直腔表面发射激光器可以包括从发射器接收光信号，将光信号转换为波形，基于波形产生读取捕获窗口，在读取捕获窗口中的第一位置采样数据，采样 在读取捕获窗口中的第二位置处的数据，并且响应于在第一位置处的采样数据与第二位置处的采样数据之间的差异，向发射机发送信号以增加光信号的功率电平，超过 阈。
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公开(公告)号：US08031819B2
公开(公告)日：2011-10-04
申请号：US11588459
申请日：2006-10-27
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , H03K3/0375 , H03K3/35613 , H03K5/135
摘要： Systems and methods for synchronizing an input signal with a substantial mitigation of race conditions and a substantial increase in resolving time are provided. One embodiment includes a system comprising a first latching device configured to latch a first output signal from the input signal and a delay element configured to receive the first output signal and output a delay signal that is a delayed version of the first output signal. The system also includes a pass-gate element configured to receive the first output signal and to output a second output signal in response to a logic state of the delay signal. The second output signal has a delayed input edge without a delayed resolving edge. The system can be configured to force the first output signal to a stable logic state in response to the first output signal having a metastable state.
摘要翻译： 提供了用于同步输入信号与大量减轻竞争条件并大大增加解析时间的系统和方法。 一个实施例包括一种系统，其包括被配置为从输入信号锁存第一输出信号的第一锁存装置和被配置为接收第一输出信号并输出作为第一输出信号的延迟版本的延迟信号的延迟元件。 该系统还包括一个通过栅极元件，配置成接收第一输出信号并响应于延迟信号的逻辑状态输出第二输出信号。 第二输出信号具有延迟的输入边沿，而没有延迟的分辨率边缘。 响应于具有亚稳态的第一输出信号，该系统可被配置为迫使第一输出信号处于稳定的逻辑状态。
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公开(公告)号：US20080101513A1
公开(公告)日：2008-05-01
申请号：US11588459
申请日：2006-10-27
IPC分类号： H04L7/00
CPC分类号： H04L7/02 , H03K3/0375 , H03K3/35613 , H03K5/135
摘要： Systems and methods for synchronizing an input signal with a substantial mitigation of race conditions and a substantial increase in resolving time are provided. One embodiment includes a system comprising a first latching device configured to latch a first output signal from the input signal and a delay element configured to receive the first output signal and output a delay signal that is a delayed version of the first output signal. The system also includes a pass-gate element configured to receive the first output signal and to output a second output signal in response to a logic state of the delay signal. The second output signal has a delayed input edge without a delayed resolving edge. The system can be configured to force the first output signal to a stable logic state in response to the first output signal having a metastable state.
摘要翻译： 提供了用于同步输入信号与大量减轻竞争条件并大大增加解析时间的系统和方法。 一个实施例包括一种系统，其包括被配置为从输入信号锁存第一输出信号的第一锁存装置和被配置为接收第一输出信号并输出作为第一输出信号的延迟版本的延迟信号的延迟元件。 该系统还包括一个通过栅极元件，配置成接收第一输出信号并响应于延迟信号的逻辑状态输出第二输出信号。 第二输出信号具有延迟的输入边沿，而没有延迟的分辨率边缘。 响应于具有亚稳态的第一输出信号，该系统可被配置为迫使第一输出信号处于稳定的逻辑状态。
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