公开(公告)号：US07358446B2

公开(公告)日：2008-04-15

申请号：US10685175

申请日：2003-10-14

Applicant: Sachin Navin Chheda ,  Ricardo E. Espinoza-Ibarra ,  Kirk Yates

Inventor： Sachin Navin Chheda ,  Ricardo E. Espinoza-Ibarra ,  Kirk Yates

IPC: H05K1/16

CPC classification number: G06F1/189

Abstract: A power distribution system comprises a flexible power connector, a printed circuit board, a power supply, and a processor mounted on the printed circuit board. The flexible power connector comprises a first end electrically connected to the processor and a second end electrically connected to the power supply. The flexible power connector is configured with a length so that the power supply is in a spaced relationship relative to the processor and the flexible power connector includes a plurality of stacked layers arranged generally parallel to each other for distributed power transmission. These layers include at least two ground layers and at least one power layer. The power layer is sandwiched between two of the at least two ground layers.

Abstract translation: 配电系统包括柔性电源连接器，印刷电路板，电源和安装在印刷电路板上的处理器。 柔性电源连接器包括电连接到处理器的第一端和电连接到电源的第二端。 柔性电源连接器被配置成具有一定长度，使得电源相对于处理器处于间隔开的关系，并且柔性电源连接器包括大体上彼此平行布置以分布式电力传输的多个堆叠层。 这些层包括至少两个接地层和至少一个功率层。 功率层夹在至少两个接地层中的两个之间。

公开(公告)号：US07182644B2

公开(公告)日：2007-02-27

申请号：US10426229

申请日：2003-04-30

Applicant: Andrew Michael Cherniski ,  Kirk Yates

Inventor： Andrew Michael Cherniski ,  Kirk Yates

IPC: H01R13/66

CPC classification number: H01R13/719 ,  H01R13/652 ,  H01R24/78 ,  H01R2103/00 ,  H01R2201/06 ,  H05K1/0231 ,  H05K1/181 ,  H05K2201/0715 ,  H05K2201/09618 ,  H05K2201/09809 ,  H05K2201/10189

Abstract: An electrical device having an enclosure in which noise is parasitically induced in a wire located in the interior of the enclosure is disclosed. The electrical device has an entry connector for mating the wire with an external connector at which a transmission line terminates for preventing the induced noise from being emitted from the device enclosure via the transmission line. The electrical device comprises a printed circuit board (PCB) adapted to be mounted adjacent to an opening in a wall of the enclosure, a receptacle, integral with the PCB, configured to mate with the external connector, a first conductive path coupling the transmission line with the wire when mated, and capacitors mounted on the printed circuit board radially disposed around the receptacle and adapted to be electrically coupled to the external connector when mated. The electrical device further comprises a second conductive path coupling the capacitors to a low potential sink.

Abstract translation: 公开了一种具有外壳的电气设备，其中噪声在位于外壳内部的导线中被寄生地感应。 电气设备具有用于将导线与外部连接器配合的入口连接器，在该连接器处传输线终止，用于防止感应噪声经由传输线从设备外壳发射。 电气设备包括适于安装在外壳壁上的开口附近的印刷电路板（PCB），与该PCB一体的插座，被配置为与外部连接器相配合，第一导电路径将传输线 并且电容器安装在放射状设置在插座周围的印刷电路板上，并且适合于在配合时电耦合到外部连接器。 电气设备还包括将电容器耦合到低电位宿的第二导电路径。

公开(公告)号：US07082488B2

公开(公告)日：2006-07-25

申请号：US10461522

申请日：2003-06-12

Applicant: Thane M. Larson ,  Kirk Yates

Inventor： Thane M. Larson ,  Kirk Yates

IPC: G06F13/00 ,  G06F21/04

CPC classification number: G06F11/0772 ,  G06F11/0727 ,  G06F11/0793 ,  H04L41/12

Abstract: Embodiments of the present invention provide a system and method for detecting if a device is coupled to an inter-integrated circuit (I2C) router and/or for resetting the device. The I2C router comprises a first I2C bus port having a presence line and/or a reset line. The I2C router further comprises a control logic coupled to and/or distributed within the first I2C bus port. The control logic may determine if a device is coupled to the I2C router as a function of a state of the presence line. The control logic may also determine if a reset condition exists. If a reset condition exists, the control logic changes the state of the reset line, thereby causing the device to reset itself.

Abstract translation: 本发明的实施例提供一种用于检测设备是否耦合到集成电路（I2C）路由器和/或用于复位设备的系统和方法。 I2C路由器包括具有存在线和/或复位线的第一I2C总线端口。 I2C路由器还包括耦合到第一I2C总线端口和/或分配在第一I2C总线端口内的控制逻辑。 作为存在线的状态的函数，控制逻辑可以确定设备是否耦合到I2C路由器。 控制逻辑还可以确定是否存在复位条件。 如果存在复位条件，则控制逻辑改变复位线的状态，从而使器件自身复位。

公开(公告)号：US20060139832A1

公开(公告)日：2006-06-29

申请号：US11026174

申请日：2004-12-29

Applicant: Kirk Yates ,  Andrew Cherniski ,  Kenneth Viloria

Inventor： Kirk Yates ,  Andrew Cherniski ,  Kenneth Viloria

IPC: H02H9/00

CPC classification number: H02H9/042

Abstract: A filter circuit in a surge protection device comprises a Y-capacitor, a first metal oxide varistor (MOV) coupled between a first line and the Y-capacitor, and a second metal oxide varistor (MOV) coupled between a second line and the Y-capacitor.

Abstract translation: 浪涌保护装置中的滤波电路包括Y电容器，耦合在第一线路和Y电容器之间的第一金属氧化物变阻器（MOV）和耦合在第二线路与Y电容器之间的第二金属氧化物变阻器（MOV） 电容器。

公开(公告)号：US20050021260A1

公开(公告)日：2005-01-27

申请号：US10606713

申请日：2003-06-26

Applicant: Naysen Robertson ,  Benjamin Percer ,  Kirk Yates

Inventor： Naysen Robertson ,  Benjamin Percer ,  Kirk Yates

IPC: G06F11/24 ,  G01R31/30 ,  G06F1/04 ,  G06F11/22 ,  G11C29/02 ,  G01R23/00

CPC classification number: G01R31/30 ,  G06F11/24 ,  G11C29/02

Abstract: The present invention provides systems and methods for performing frequency margin testing of a computer system, such as a server. A system of the invention can include a controller, e.g., a BMC, internal to the computer system and a digital frequency synthesizer that can communicate with the controller and can apply clock frequency to marginable components of the computer system. In response to commands from the controller, the synthesizer generates one or more test frequencies that are applied to one or more of the marginable components. The response of the system to each of the test frequencies is then monitored.

Abstract translation: 本发明提供了用于对诸如服务器的计算机系统执行频率裕度测试的系统和方法。 本发明的系统可以包括控制器，例如计算机系统内部的BMC，以及数字频率合成器，其可以与控制器通信，并且可以将时钟频率应用于计算机系统的可容易的组件。 响应于来自控制器的命令，合成器产生应用于一个或多个可容易组件的一个或多个测试频率。 然后监测系统对每个测试频率的响应。

公开(公告)号：US07053691B2

公开(公告)日：2006-05-30

申请号：US10431102

申请日：2003-05-06

Applicant: Kirk Yates ,  Andrew M. Cherniski ,  Rodrigo Bainotti

Inventor： Kirk Yates ,  Andrew M. Cherniski ,  Rodrigo Bainotti

IPC: H03K17/62 ,  H03K17/76 ,  H03K17/693 ,  H03K17/735

CPC classification number: H03K17/693 ,  H02J1/00 ,  H02J9/061 ,  H03K17/302

Abstract: A circuit that allows selection of a power source among a plurality of power sources is disclosed. In an embodiment, either one or both voltage sources Vaux and Vapp may be available in a system. If both sources are available, then the circuit enables the system to use source Vaux. However, if only one of the two sources is available, then the circuit enables the system to use that available source.

Abstract translation: 公开了允许在多个电源中选择电源的电路。 在一个实施例中，系统中可以使用一个或两个电压源V SUB和V SUB应用。 如果两个源均可用，则该电路使系统能够使用源V辅助。 但是，如果两个源中只有一个可用，则该电路使系统能够使用该可用源。

公开(公告)号：US20050078463A1

公开(公告)日：2005-04-14

申请号：US10685175

申请日：2003-10-14

Applicant: Sachin Chheda ,  Ricardo Espinoza-Ibarra ,  Kirk Yates

Inventor： Sachin Chheda ,  Ricardo Espinoza-Ibarra ,  Kirk Yates

IPC: G06F1/18 ,  H05K7/06

CPC classification number: G06F1/189

Abstract: A power distribution system comprises a flexible power connector, a printed circuit board, a power supply, and a processor mounted on the printed circuit board. The flexible power connector comprises a first end electrically connected to the processor and a second end electrically connected to the power supply. The flexible power connector is configured with a length so that the power supply is in a spaced relationship relative to the processor and the flexible power connector includes a plurality of stacked layers arranged generally parallel to each other for distributed power transmission. These layers include at least two ground layers and at least one power layer. The power layer is sandwiched between two of the at least two ground layers.

Abstract translation: 配电系统包括柔性电源连接器，印刷电路板，电源和安装在印刷电路板上的处理器。 柔性电源连接器包括电连接到处理器的第一端和电连接到电源的第二端。 柔性电源连接器被配置成具有一定长度，使得电源相对于处理器处于间隔开的关系，并且柔性电源连接器包括大体上彼此平行布置以分布式电力传输的多个堆叠层。 这些层包括至少两个接地层和至少一个功率层。 功率层夹在至少两个接地层中的两个之间。

公开(公告)号：US20050002384A1

公开(公告)日：2005-01-06

申请号：US10461530

申请日：2003-06-12

Applicant: Thane Larson ,  Kirk Yates ,  Kirk Bresniker

Inventor： Thane Larson ,  Kirk Yates ,  Kirk Bresniker

IPC: G06F13/38 ,  G06F3/00 ,  G06F13/14 ,  G06F13/42 ,  H04L13/08

CPC classification number: G06F13/4291

Abstract: A method of transmitting data through an I2C router from a source port to a destination port, the method comprising: receiving data in a first I2C source port buffer of the I2C router; capturing the I2C destination port before the first I2C source port buffer has overflowed; and transmitting the data from the first I2C source port buffer to the I2C destination port while restricting transmission from the second I2C source port buffer to the I2C destination port.

Abstract translation: 一种通过I2C路由器将数据从源端口传输到目标端口的方法，所述方法包括：在所述I2C路由器的第一I2C源端口缓冲器中接收数据; 在第一个I2C源端口缓冲区溢出之前捕获I2C目标端口; 并将数据从第一个I2C源端口缓冲区传输到I2C目标端口，同时限制从第二个I2C源端口缓冲区传输到I2C目标端口。

公开(公告)号：US07652896B2

公开(公告)日：2010-01-26

申请号：US11027431

申请日：2004-12-29

Applicant: Sachin Navin Chheda ,  Kirk Yates ,  Nitin C. Bhagwath

Inventor： Sachin Navin Chheda ,  Kirk Yates ,  Nitin C. Bhagwath

IPC: H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0222 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/184 ,  H05K3/4046 ,  H05K2201/09645 ,  H05K2201/09809 ,  H05K2201/09836 ,  H05K2201/10893 ,  Y10T29/49139

Abstract: A component for insertion into a hole in a multiple-layer substrate enables impedance matching of the substrate. The component comprises a conductive ground core arranged to extend through multiple-layers of the substrate when the component is inserted, a dielectric layer laterally encasing the conductive ground core, and a signal conductor layer coupled lateral to the dielectric layer.

Abstract translation: 用于插入多层衬底中的孔的部件能够使衬底阻抗匹配。 该部件包括导电接地芯，该导电接地芯被布置成当插入元件时延伸穿过基板的多层，横向封装导电接地芯的电介质层和与电介质层横向耦合的信号导体层。

公开(公告)号：US07630304B2

公开(公告)日：2009-12-08

申请号：US10461080

申请日：2003-06-12

Applicant: Thane M. Larson ,  Kirk Yates

Inventor： Thane M. Larson ,  Kirk Yates

IPC: H04L12/26

CPC classification number: G06F11/2221 ,  G06F13/4282

Abstract: A method of recovering overflowed data at a first I2C source port buffer on an I2C router having a second I2C source port buffer and a destination port I2C bus. The method comprises: requesting resend of said overflowed data to the first I2C source port buffer; receiving the overflowed data at the first I2C source port buffer; capturing the destination port I2C bus and transmitting all data from the first I2C source port buffer to the destination port I2C bus.

Abstract translation: 一种在具有第二个I2C源端口缓冲器和目标端口I2C总线的I2C路由器上的第一个I2C源端口缓冲器上恢复溢出数据的方法。 该方法包括：请求将所述溢出的数据重新发送到第一个I2C源端口缓冲器; 在第一个I2C源端口缓冲器处接收溢出的数据; 捕获目标端口I2C总线，并将所有数据从第一个I2C源端口缓冲区传输到目标端口I2C总线。