公开(公告)号：US20120170068A1

公开(公告)日：2012-07-05

申请号：US13344167

申请日：2012-01-05

申请人： Junichi Ikeda ,  Noriyuki Terao ,  Satoru Numakura ,  Hiroyuki Takahashi ,  Tetsuya Satoh ,  Koji Takeo ,  Hideaki Yamamoto ,  Mitsuru Suzuki

发明人： Junichi Ikeda ,  Noriyuki Terao ,  Satoru Numakura ,  Hiroyuki Takahashi ,  Tetsuya Satoh ,  Koji Takeo ,  Hideaki Yamamoto ,  Mitsuru Suzuki

IPC分类号： G06K15/02

CPC分类号： G06K15/02 ,  G06K15/1801 ,  G06K15/1814 ,  G06K15/1856 ,  G06K15/1863

摘要： An image forming apparatus receives raster image data transferred from an external device and forms an image on the basis of the received raster image data. The apparatus includes a processor that controls a transfer of the raster image data from the external device, a first memory connected to the processor through a first bus is used as a working area of the processor, a second memory that stores the raster image data, a memory control unit connected to the second memory through a second bus controls an operation of writing and reading the raster image data in and from the second memory, a printer engine that forms an image on the basis of the raster image data, and an engine control unit that reads the raster image data from the second memory through the memory control unit and supplies the printer engine with the read raster image data.

摘要翻译： 图像形成装置接收从外部装置传送的光栅图像数据，并根据所接收的光栅图像数据形成图像。 该装置包括控制来自外部设备的光栅图像数据的传送的处理器，将通过第一总线连接到处理器的第一存储器用作处理器的工作区域，存储光栅图像数据的第二存储器， 通过第二总线连接到第二存储器的存储器控​​制单元控制在第二存储器中写入和读取光栅图像数据的操作，基于光栅图像数据形成图像的打印机引擎，以及引擎 控制单元，其通过存储器控制单元从第二存储器读取光栅图像数据，并向打印机引擎提供读取的光栅图像数据。

公开(公告)号：US07536489B2

公开(公告)日：2009-05-19

申请号：US11511477

申请日：2006-08-29

申请人： Koji Oshikiri ,  Noriyuki Terao ,  Junichi Ikeda ,  Koji Takeo

发明人： Koji Oshikiri ,  Noriyuki Terao ,  Junichi Ikeda ,  Koji Takeo

IPC分类号： H04J3/16 ,  H04J3/24 ,  G06F3/00 ,  G06F5/00

CPC分类号： G06F13/4278 ,  G06F2213/0026

摘要： An information processing system includes a high-speed serial bus that transmits and receives data independently over communication channels via a tree-structured network including a point-to-point connection, and a control unit that issues a request command based on a request synchronization signal for data with a timing constraint on line synchronous transfer by a line synchronization signal to transmit a plurality of data, including the data with the timing constraint, simultaneously via the high-speed serial bus.

摘要翻译： 一种信息处理系统，包括：高速串行总线，其经由包括点对点连接的树结构化网络在通信信道上独立地发送和接收数据;以及控制单元，其基于请求同步信号发出请求命令 对于具有通过线路同步信号的线路同步传输的定时约束的数据，以经由高速串行总线同时发送包括具有定时约束的数据的多个数据。

公开(公告)号：US20060227143A1

公开(公告)日：2006-10-12

申请号：US11399440

申请日：2006-04-07

申请人： Yutaka Maita ,  Junichi Ikeda ,  Satoru Numakura ,  Atsuhiro Oizumi ,  Koji Oshikiri ,  Tohru Sasaki ,  Yasuyuki Shindoh ,  Koji Takeo ,  Noriyuki Terao

发明人： Yutaka Maita ,  Junichi Ikeda ,  Satoru Numakura ,  Atsuhiro Oizumi ,  Koji Oshikiri ,  Tohru Sasaki ,  Yasuyuki Shindoh ,  Koji Takeo ,  Noriyuki Terao

IPC分类号： G06T1/00

CPC分类号： H04N1/00236

摘要： An image forming apparatus includes an image input device that reads an image to obtain image data and a printer engine that forms an image on a medium based on image data. A bus of a PCI Express standard is used to transfer data. Storage areas serving as end points of the standard and hardware resources that transmit data and receive image data to and from the storage areas are connected to an identical switch according to the PCI Express standard. Specifically, an input/output area, an image input device, and a printer engine are connected to one switch, and a storage area, a compressor, and a hard disk is connected to another switch.

摘要翻译： 图像形成装置包括：图像输入装置，其读取图像以获得图像数据;以及打印机引擎，其基于图像数据在介质上形成图像。 PCI Express标准的总线用于传输数据。 作为向存储区域发送数据和从存储区域接收图像数据的标准和硬件资源的端点的存储区域根据PCI Express标准连接到相同的交换机。 具体地，输入/输出区域，图像输入装置和打印机引擎连接到一个开关，并且存储区域，压缩器和硬盘连接到另一个开关。

公开(公告)号：US20060209722A1

公开(公告)日：2006-09-21

申请号：US11327426

申请日：2006-01-09

申请人： Koji Takeo ,  Noriyuki Terao ,  Junichi Ikeda ,  Koji Oshikiri

发明人： Koji Takeo ,  Noriyuki Terao ,  Junichi Ikeda ,  Koji Oshikiri

IPC分类号： H04L12/28

CPC分类号： H04L12/2854

摘要： A data transferring system, in which processes to match settings between devices mutually communicating are simplified, software for the processes is also simplified, and the amount of data to be processed is reduced, is disclosed. In a data transferring system of the PCI Express standard, when settings between facing ports of a switch and an end point are changed, a setting change is transmitted to the port of the end point being one of the facing ports by a configuration request. The port of the end point transmits the setting change to the port of the switch by a message request and the port of the switch executes the setting change. The port of the switch sends a completion message signifying the setting change completion to the port of the end point by a message request. The port of the end point executes the setting change.

摘要翻译： 公开了一种数据传送系统，其中相互通信的设备之间的设置匹配的过程被简化，用于处理的软件也被简化，并且减少了要处理的数据量。 在PCI Express标准的数据传输系统中，当交换机的相对端口和端点之间的设置发生变化时，通过配置请求将设置更改发送到作为其中一个端口的端点的端口。 终端端口通过消息请求将设置更改发送到交换机的端口，交换机的端口执行设置更改。 交换机的端口通过消息请求向终端的端口发送表示设置更改完成的完成消息。 终点端口执行设置更改。

公开(公告)号：US20060171300A1

公开(公告)日：2006-08-03

申请号：US11332203

申请日：2006-01-17

申请人： Koji Oshikiri ,  Junichi Ikeda ,  Koji Takeo ,  Noriyuki Terao

发明人： Koji Oshikiri ,  Junichi Ikeda ,  Koji Takeo ,  Noriyuki Terao

IPC分类号： H04J3/14

CPC分类号： G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

摘要： A data transferring system based on the PCI Express standard in which power saving is realized is disclosed. In the data transferring system, a data transferring device transfers image data based on the PCI Express standard by synchronizing with a line synchronizing signal LSYNC. At this time, the data transferring device causes a period between packets (image data) to be transferred in one line cycle of the line synchronizing signal LSYNC to be shorter than a transition period “t1” which is required to transit from a link state L0 to a link state L0s and from the link state L0s to the link state L0. With this, the number of the transition periods “t1” is reduced and the period of the link state L0s is made long.

摘要翻译： 公开了一种基于实现省电的PCI Express标准的数据传输系统。 在数据传送系统中，数据传送装置通过与行同步信号LSYNC同步，基于PCI Express标准传送图像数据。 此时，数据传送装置使得在行同步信号LSYNC的一个行周期中传送的分组（图像数据）之间的周期短于从链接状态过渡所需的过渡期间“t 1” L 0到链路状态L 0 s，并且从链路状态L 0 s到链路状态L 0。 由此，过渡期间“t 1”的数量减少，链路状态L 0 s的周期变长。

公开(公告)号：US09361249B2

公开(公告)日：2016-06-07

申请号：US14566001

申请日：2014-12-10

申请人： Tetsuya Satoh ,  Noriyuki Terao ,  Koji Takeo ,  Hideaki Yamamoto ,  Junichi Ikeda ,  Satoru Numakura ,  Mitsuru Suzuki ,  Hiroyuki Takahashi ,  Kohki Sasaki

发明人： Tetsuya Satoh ,  Noriyuki Terao ,  Koji Takeo ,  Hideaki Yamamoto ,  Junichi Ikeda ,  Satoru Numakura ,  Mitsuru Suzuki ,  Hiroyuki Takahashi ,  Kohki Sasaki

IPC分类号： G06F13/00 ,  G06F13/12 ,  G06F13/40

CPC分类号： G06F13/128 ,  G06F13/405

摘要： A communication apparatus for carrying out communications to and from an external apparatus that includes a first interconnecting unit and a first non-transparent port and effects an interconnection for communications via the first non-transparent port is provided. The communication apparatus includes a second interconnecting unit that includes a second non-transparent port communicably connected to the first non-transparent port. The second interconnecting unit effects an interconnection for communications via the second non-transparent port. The second interconnecting unit performs, when the communication apparatus carries out communications to and from the external apparatus, address translation between an address for use by the communication apparatus and an address for use by the second non-transparent port.

公开(公告)号：US09166933B2

公开(公告)日：2015-10-20

申请号：US13542139

申请日：2012-07-05

申请人： Satoru Numakura ,  Junichi Ikeda ,  Mitsuru Suzuki ,  Koji Takeo ,  Tetsuya Satoh ,  Hiroyuki Takahashi

发明人： Satoru Numakura ,  Junichi Ikeda ,  Mitsuru Suzuki ,  Koji Takeo ,  Tetsuya Satoh ,  Hiroyuki Takahashi

IPC分类号： G11C7/10 ,  H04L12/861 ,  G11C8/16 ,  G06F7/00 ,  H04L12/879

CPC分类号： H04L49/9042 ,  G06F7/00 ,  G11C8/16 ,  H04L49/901

摘要： A memory control apparatus that controls writing and reading of data to/from a memory. The memory control apparatus includes: a sequence control unit that receives a packet sequence including a write packet including a write request of data and a read packet including a read request of the data, and changes an arrangement of the write packet and the read packet included in the packet sequence so that a first predetermined number of write packets are arranged successively and a second predetermined number of read packets are arranged successively; and a command output unit that receives the packet sequence from the sequence control unit, and outputs a write command according to the write packet and an a read command according to the read packet to the memory, in accordance with an order of arrangement of the write packet and the read packet.

摘要翻译： 一种用于控制向/从存储器写入和读取数据的存储器控​​制装置。 存储器控制装置包括：序列控制单元，其接收包括包括数据的写入请求的写入包和包含数据的读取请求的读取包的数据包序列，并且改变写入数据包和包含的读取数据包的配置 在分组序列中，使得第一预定数量的写分组被连续地排列，并且第二预定数量的读分组被依次布置; 以及命令输出单元，其从顺序控制单元接收分组序列，并且根据写入分组和根据读取的分组的读取命令，根据写入的顺序将顺序输出到存储器 包和读包。

公开(公告)号：US20130016726A1

公开(公告)日：2013-01-17

申请号：US13542139

申请日：2012-07-05

申请人： Satoru NUMAKURA ,  Junichi IKEDA ,  Mitsuru SUZUKI ,  Koji TAKEO ,  Tetsuya SATOH ,  Hiroyuki TAKAHASHI

发明人： Satoru NUMAKURA ,  Junichi IKEDA ,  Mitsuru SUZUKI ,  Koji TAKEO ,  Tetsuya SATOH ,  Hiroyuki TAKAHASHI

IPC分类号： H04L12/56

CPC分类号： H04L49/9042 ,  G06F7/00 ,  G11C8/16 ,  H04L49/901

摘要： A memory control apparatus that controls writing and reading of data to/from a memory. The memory control apparatus includes: a sequence control unit that receives a packet sequence including a write packet including a write request of data and a read packet including a read request of the data, and changes an arrangement of the write packet and the read packet included in the packet sequence so that a first predetermined number of write packets are arranged successively and a second predetermined number of read packets are arranged successively; and a command output unit that receives the packet sequence from the sequence control unit, and outputs a write command according to the write packet and an a read command according to the read packet to the memory, in accordance with an order of arrangement of the write packet and the read packet.

摘要翻译： 一种用于控制向/从存储器写入和读取数据的存储器控​​制装置。 存储器控制装置包括：序列控制单元，其接收包括包括数据的写入请求的写入包和包含数据的读取请求的读取包的数据包序列，并且改变写入数据包和包含的读取数据包的配置 在分组序列中，使得第一预定数量的写分组被连续地排列，并且第二预定数量的读分组被依次布置; 以及命令输出单元，其从顺序控制单元接收分组序列，并且根据写入分组和根据读取的分组的读取命令，根据写入的顺序将顺序输出到存储器 包和读包。

公开(公告)号：US20100067042A1

公开(公告)日：2010-03-18

申请号：US12461850

申请日：2009-08-26

申请人： Junichi Ikeda ,  Koji Oshikiri ,  Koji Takeo ,  Tetsuya Sato ,  Yosuke Kawamura ,  Hiroyuki Takahashi

发明人： Junichi Ikeda ,  Koji Oshikiri ,  Koji Takeo ,  Tetsuya Sato ,  Yosuke Kawamura ,  Hiroyuki Takahashi

IPC分类号： G06F15/00

CPC分类号： H04N1/2307 ,  H04N1/00912 ,  H04N1/00933 ,  H04N1/32 ,  H04N1/32582 ,  H04N1/32587 ,  H04N1/32593 ,  H04N2201/0082

摘要： A plotter repeats a process of standing by until the next line synchronization timing after data transfer for one line and transferring DMAC control information requesting data transfer for one line to an MCH for each line synchronization timing whereby image data for one page is transferred. Therefore, data transfer from the MCH to the plotter is processed by continuous posted requests, so that float with respect to a line period can be made longer without transmitting a plurality of data transfer requests from the plotter to the MCH in the split method. Thus, a high data transfer performance can be realized with an inexpensive circuit because the cost for mounting a buffer memory or the like on the circuit is not needed.

摘要翻译： 绘图仪重复进行直到一行的数据传送之后的下一行同步定时的处理，并且将用于一行的DMAC控制信息请求数据传送到每个行同步定时的MCH，由此传送一页的图像数据。 因此，通过连续发送的请求来处理从MCH到绘图机的数据传送，使得可以使得相对于行周期的浮动可以更长，而在分割方法中不将多个数据传送请求从绘图仪发送到MCH。 因此，由于不需要在电路上安装缓冲存储器等的成本，所以可以用廉价的电路实现高数据传输性能。

公开(公告)号：US20060114918A1

公开(公告)日：2006-06-01

申请号：US11125207

申请日：2005-05-10

申请人： Junichi Ikeda ,  Koji Oshikiri ,  Atsuhiro Oizumi ,  Yutaka Maita ,  Satoru Numakura ,  Noriyuki Terao ,  Yasuyuki Shindoh ,  Tohru Sasaki ,  Koji Takeo

发明人： Junichi Ikeda ,  Koji Oshikiri ,  Atsuhiro Oizumi ,  Yutaka Maita ,  Satoru Numakura ,  Noriyuki Terao ,  Yasuyuki Shindoh ,  Tohru Sasaki ,  Koji Takeo

IPC分类号： H04L12/56

CPC分类号： H04L45/48 ,  H04L45/02

摘要： A data transfer system using a high-speed serial interface system that forms a tree structure in which point-to-point communication channels are established for data sending and data receiving independently is provided. The data transfer system includes plural end points each having plural upper ports each of which is connected to a switch of an upper side, wherein each end point includes a port selecting part for selecting a port to be used according to an operation mode of the data transfer system so as to dynamically change the tree structure.

摘要翻译： 提供了一种数据传输系统，其使用形成树形结构的高速串行接口系统，其中为了数据发送和数据接收独立地建立点对点通信信道。 数据传输系统包括多个端点，每个端点具有多个上端口，每个端口连接到上侧的开关，其中每个端点包括端口选择部分，用于根据数据的操作模式选择要使用的端口 传输系统，以动态地改变树结构。