公开(公告)号：US08525712B2

公开(公告)日：2013-09-03

申请号：US13195144

申请日：2011-08-01

Applicant: Takashi Oshima ,  Tatsuji Matsuura ,  Naoki Yada ,  Takahiro Miki ,  Akihiro Kitagawa ,  Tetsuo Matsui ,  Kunihiko Usui

Inventor： Takashi Oshima ,  Tatsuji Matsuura ,  Naoki Yada ,  Takahiro Miki ,  Akihiro Kitagawa ,  Tetsuo Matsui ,  Kunihiko Usui

IPC: H03M1/10

CPC classification number: H03M1/1033 ,  G01S7/4021 ,  G01S13/931 ,  H03M1/167 ,  H03M1/442

Abstract: To improve resolution of a built-in A/D converter by reducing the area occupied by a chip of the built-in A/D converter in a semiconductor integrated circuit that is mounted in an on-vehicle millimeter wave radar device and which incorporates an A/D converter and an MPU. In the semiconductor integrated circuit, a plurality of reception signals of the radar device is A/D-converted by a single digital correction type A/D converter. The digital correction type A/D converter of the single A/D converter is a foreground digital correction type A/D converter that sequentially A/D-converts the reception signals output from a multiplexer of a receiving interface. The single A/D converter includes a pipeline type A/D converter having a plurality of cascade-coupled converters. The semiconductor integrated circuit comprises a correction signal generating unit, a digital correction D/A converter, and a digital correction unit for digital correction.

Abstract translation: 通过在安装在车载毫米波雷达装置中的半导体集成电路中减小内置A / D转换器的芯片所占用的面积来提高内置A / D转换器的分辨率， A / D转换器和MPU。 在半导体集成电路中，由单个数字校正型A / D转换器对雷达装置的多个接收信号进行A / D转换。 单个A / D转换器的数字校正型A / D转换器是从接收接口的多路复用器输出的接收信号顺序进行A / D转换的前景数字校正型A / D转换器。 单个A / D转换器包括具有多个级联耦合转换器的流水线型A / D转换器。 半导体集成电路包括校正信号生成单元，数字校正D / A转换器和用于数字校正的数字校正单元。

公开(公告)号：US20120038498A1

公开(公告)日：2012-02-16

申请号：US13195144

申请日：2011-08-01

Applicant: Takashi OSHIMA ,  Tatsuji MATSUURA ,  Naoki YADA ,  Takahiro MIKI ,  Akihiro KITAGAWA ,  Tetsuo MATSUI ,  Kunihiko USUI

Inventor： Takashi OSHIMA ,  Tatsuji MATSUURA ,  Naoki YADA ,  Takahiro MIKI ,  Akihiro KITAGAWA ,  Tetsuo MATSUI ,  Kunihiko USUI

IPC: H03M1/06 ,  H03M1/00

CPC classification number: H03M1/1033 ,  G01S7/4021 ,  G01S13/931 ,  H03M1/167 ,  H03M1/442

Abstract: To improve resolution of a built-in A/D converter by reducing the area occupied by a chip of the built-in A/D converter in a semiconductor integrated circuit that is mounted in an on-vehicle millimeter wave radar device and which incorporates an A/D converter and an MPU. In the semiconductor integrated circuit, a plurality of reception signals of the radar device is A/D-converted by a single digital correction type A/D converter. The digital correction type A/D converter of the single A/D converter is a foreground digital correction type A/D converter that sequentially A/D-converts the reception signals output from a multiplexer of a receiving interface. The single A/D converter includes a pipeline type A/D converter having a plurality of cascade-coupled converters. The semiconductor integrated circuit comprises a correction signal generating unit, a digital correction D/A converter, and a digital correction unit for digital correction.

Abstract translation: 通过在安装在车载毫米波雷达装置中的半导体集成电路中减小内置A / D转换器的芯片所占用的面积来提高内置A / D转换器的分辨率， A / D转换器和MPU。 在半导体集成电路中，由单个数字校正型A / D转换器对雷达装置的多个接收信号进行A / D转换。 单个A / D转换器的数字校正型A / D转换器是从接收接口的多路复用器输出的接收信号顺序进行A / D转换的前景数字校正型A / D转换器。 单个A / D转换器包括具有多个级联耦合转换器的流水线型A / D转换器。 半导体集成电路包括校正信号生成单元，数字校正D / A转换器和用于数字校正的数字校正单元。

公开(公告)号：US5394148A

公开(公告)日：1995-02-28

申请号：US026038

申请日：1993-03-04

Applicant: Tatsuji Matsuura ,  Imaizumi Eiki ,  Kunihiko Usui ,  Takanobu Anbo

Inventor： Tatsuji Matsuura ,  Imaizumi Eiki ,  Kunihiko Usui ,  Takanobu Anbo

IPC: H03M1/10 ,  H03M1/14 ,  H03M1/36 ,  H03M1/42

CPC classification number: H03M1/146 ,  H03M1/365

Abstract: A high speed, accurate AD converter operable at low supply voltage, even with low gain amplifiers, particularly for a serial-parallel or pipelined AD converter, has a sub AD converter in each block of the second and subsequent stages provided with an adjuster for adjusting the full scale reference voltage in accordance with the gain of the error amplifier of the preceding stage. Analog switches are rendered immune to low operating voltage by being supplied separate voltage higher than the supply voltage of the other components in their circuit.

Abstract translation: 即使使用低增益放大器，特别是串并联或流水线式AD转换器，也可以在低电源电压下工作的高速，精确的AD转换器在第二级和后续级的每个模块中都有一个副AD转换器，它设有调节器 根据前级误差放大器的增益，满量程参考电压。 模拟开关通过提供高于其电路中其他组件的电源电压的单独电压而免于低工作电压。

公开(公告)号：US5113090A

公开(公告)日：1992-05-12

申请号：US574087

申请日：1990-08-29

Applicant: Eiki Imaizumi ,  Kunihiko Usui ,  Tatsuji Matsuura ,  Toshiro Tsukada ,  Seiichi Ueda ,  Hiroshi Sato

Inventor： Eiki Imaizumi ,  Kunihiko Usui ,  Tatsuji Matsuura ,  Toshiro Tsukada ,  Seiichi Ueda ,  Hiroshi Sato

IPC: H03M1/34 ,  H03K5/08 ,  H03K5/24

CPC classification number: H03K5/2481

Abstract: A voltage comparator is provided including a differential amplifier, first, second and third switches, and first and second capacitors. A fourth switch is connected in series between the second and third switches and an input terminal of the differential amplifier. A first input voltage is sampled and held at the first capacitor through the first switch and at the second capacitor through the second and fourth switches, respectively. Thereafter, since the third switch is turned on and the fourth switch is turned off, the first input voltage is sampled and held at the input capacitor of the differential amplifier. Thereafter, the third switch is turned off and the fourth switch turned on. As a result, an on and off operation of the fourth switch is controlled so that a second input voltage which has been sampled at the second capacitor immediately before the switch is turned off is applied to the input capacitor of the differential amplifier.

Abstract translation: 提供电压比较器，其包括差分放大器，第一，第二和第三开关以及第一和第二电容器。 第四开关串联连接在第二和第三开关和差分放大器的输入端之间。 第一输入电压通过第一开关和第二电容器分别通过第二和第四开关被采样并保持在第一电容器处。 此后，由于第三开关导通，第四开关断开，所以第一输入电压被采样并保持在差分放大器的输入电容器。 此后，第三开关断开，第四开关导通。 结果，控制第四开关的接通和断开操作，使得在开关断开之前在第二电容器处被采样的第二输入电压被施加到差分放大器的输入电容器。

公开(公告)号：US5194866A

公开(公告)日：1993-03-16

申请号：US793574

申请日：1991-11-18

Applicant: Eiki Imaizumi ,  Kunihiko Usui ,  Tatsuji Matsuura

Inventor： Eiki Imaizumi ,  Kunihiko Usui ,  Tatsuji Matsuura

IPC: H03M1/14 ,  H03M1/36

CPC classification number: H03M1/144 ,  H03M1/365

Abstract: A resistor-string divided into plural sets of unit-resistors generates plural reference voltages for the upper bits, while each divided set generates plural reference voltages for the lower bits. A first and second differential input are generated in direct and inverse proportion to the analog input voltage. Differential comparators for the upper bits compare two differential voltages from between the two reference voltages and the first and second differential input votlages. Two of the divided sets are selected according to the upper bit digital value and one reference voltage from each selected set is switched to a differential comparator for the lower order bits. Lower order bit comparison is similar to the high order comparison described above. Final digital value is obtained by linking the upper and lower bits digital value.

Abstract translation: 分成多组单位电阻的电阻串为高位产生多个参考电压，而每个划分的集合产生用于较低位的多个参考电压。 第一和第二差分输入以与模拟输入电压成直比的方式产生。 高位差分比较器比较两个参考电压和第一和第二差分输入电平之间的两个差分电压。 根据高位数字值选择两个分割组，并且将来自每个选定组的一个参考电压切换到低位位的差分比较器。 较低阶比较类似于上述高阶比较。 通过连接上位和下位数字值获得最终数字值。

公开(公告)号：US5274377A

公开(公告)日：1993-12-28

申请号：US907524

申请日：1992-07-02

Applicant: Tatsuji Matsuura ,  Eiki Imaizumi ,  Kunihiko Usui

Inventor： Tatsuji Matsuura ,  Eiki Imaizumi ,  Kunihiko Usui

IPC: H03M1/14 ,  H03M1/06 ,  H03M1/16 ,  H03M1/42

CPC classification number: H03M1/069 ,  H03M1/167

Abstract: There is disclosed a pipelined A/D converter including a plurality of A/D-D/A sub-blocks and one A/D sub-block successively connected in cascade form to determine a conversion output by several partial bits beginning from the most significant bit. Each of A/D-D/A sub-blocks includes a sample-and-hold circuit for successively sampling and holding an input analog signal fed to the sub-block, a partial A/D converter for performing A/D conversion on a hold output of this sample-and-hold circuit, a latch circuit for latching outputs of the partial A/D converter, a D/A converter for inversely converting outputs of the latch circuit to an analog signal, and a chopper amplifier for sampling the hold output of the sample-and-hold circuit with a delay of half a period, amplifying a difference between the sampled value and the inverse conversion output of the D/A converter during a succeeding interval of amplify mode, and outputting the amplified difference to a sub-block of a succeeding stage as a conversion residue.

Abstract translation: 公开了一种流水线式A / D转换器，包括多个A / D-D / A子块和一个依次以级联形式连接的A / D子块，以确定从最高有效位开始的几个部分位的转换输出。 每个A / DD / A子块包括用于连续采样和保持馈送到子块的输入模拟信号的采样和保持电路，用于在保持输出上执行A / D转换的部分A / D转换器 该采样保持电路用于锁存部分A / D转换器的输出的锁存电路，用于将锁存电路的输出反向转换为模拟信号的D / A转换器，以及用于对保持输出进行采样的斩波放大器 的采样保持电路，在放大模式的后续间隔期间放大D / A转换器的采样值和逆变换输出之间的差，并将放大的差值输出到子 - 作为转化残基的后续阶段。