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    Memory Devices Having Adjustable Refresh Cycles Responsive to Temperature Changes
    1.
    发明申请
    Memory Devices Having Adjustable Refresh Cycles Responsive to Temperature Changes 有权
    具有响应于温度变化的可调节刷新周期的存储器件

    公开(公告)号：US20110116327A1

    公开(公告)日：2011-05-19

    申请号：US12941500

    申请日：2010-11-08

    申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

    发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

    IPC分类号： G11C7/00 ,  G11C11/402

    CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

    摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

    摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

    Semiconductor IC including pad for wafer test and method of testing wafer including semiconductor IC
    2.
    发明授权
    Semiconductor IC including pad for wafer test and method of testing wafer including semiconductor IC 失效
    半导体IC包括用于晶片测试的焊盘和包括半导体IC的晶片测试方法

    公开(公告)号：US07716550B2

    公开(公告)日：2010-05-11

    申请号：US11938480

    申请日：2007-11-12

    申请人： Kwang-Sook Noh

    发明人： Kwang-Sook Noh

    IPC分类号： G06F11/00

    CPC分类号： G06F11/263

    摘要： Provided are a semiconductor integrated circuit (IC) including a pad for a wafer test and a method of testing a wafer including a semiconductor IC. The semiconductor IC includes a first address generator, a second address generator, and an address output unit. The first address generator generates a normal address having (M+N) bits or a first test address having M bits corresponding to voltages applied to a plurality of address pads. The second address generator generates a second test address having N bits corresponding to a voltage applied to an additional pad. Therefore, according to the semiconductor IC and the wafer test method, an additional pad is provided to generate an N-bit test address in wafer test mode such that the number of pads needed to test a device can be reduced. As a result, more semiconductor ICs can be tested simultaneously.

    摘要翻译： 提供了一种包括用于晶片测试的焊盘的半导体集成电路（IC）和测试包括半导体IC的晶片的方法。 半导体IC包括第一地址发生器，第二地址发生器和地址输出单元。 第一地址发生器产生具有（M + N）位的正常地址或具有对应于施加到多个地址焊盘的电压的M位的第一测试地址。 第二地址发生器产生具有对应于施加到附加焊盘的电压的N位的第二测试地址。 因此，根据半导体IC和晶片测试方法，提供附加焊盘以在晶片测试模式中产生N位测试地址，使得可以减少测试器件所需的焊盘数量。 因此，可以同时测试更多的半导体IC。

    Integrated circuit device and method for applying different types of signals to internal circuit via one pin
    3.
    发明授权
    Integrated circuit device and method for applying different types of signals to internal circuit via one pin 有权
    集成电路器件和方法，通过一个引脚将不同类型的信号应用于内部电路

    公开(公告)号：US06876564B2

    公开(公告)日：2005-04-05

    申请号：US10689403

    申请日：2003-10-20

    申请人： Kyoung-hwan Kwon ,  Kwang-sook Noh

    发明人： Kyoung-hwan Kwon ,  Kwang-sook Noh

    IPC分类号： G01R31/28 ,  G11C11/40 ,  G11C29/12 ,  H01L21/822 ,  H01L27/04 ,  H03K19/173 ,  G11C5/06

    CPC分类号： H03K19/1732

    摘要： Provided are an integrated circuit and a method thereof, in which different types of signals can be applied to an internal circuit via one pin. The integrated circuit device includes a distribution unit, a level fixing unit, and an activation unit. The distribution unit receives and outputs a first input signal input via the first input pin, and receives and outputs a second input signal input via the first input pin in response to a control signal. The level fixing unit receives the first input signal from the distribution unit and applies a signal having the same voltage level as the first input signal to a first internal circuit in response to the control signal. The activation unit receives the second input signal input via the second input pin and then applies the second input signal to a second internal circuit or applies the second input signal output from the distribution unit to the second internal circuit in response to the control signal.

    摘要翻译： 提供了一种集成电路及其方法，其中可以通过一个引脚将不同类型的信号施加到内部电路。 集成电路装置包括分配单元，电平固定单元和激活单元。 分配单元接收并输出经由第一输入引脚输入的第一输入信号，并且响应于控制信号接收并输出经由第一输入引脚输入的第二输入信号。 电平固定单元从分配单元接收第一输入信号，并响应于控制信号将与第一输入信号具有相同电压电平的信号施加到第一内部电路。 激活单元接收经由第二输入引脚输入的第二输入信号，然后将第二输入信号施加到第二内部电路，或者响应于控制信号将从分配单元输出的第二输入信号施加到第二内部电路。

    Data receivers for reproducing data input signals and methods for detecting data signals in data input receivers
    4.
    发明授权
    Data receivers for reproducing data input signals and methods for detecting data signals in data input receivers 失效
    用于再现数据输入信号的数据接收器和用于检测数据输入接收器中的数据信号的方法

    公开(公告)号：US06590429B2

    公开(公告)日：2003-07-08

    申请号：US10086675

    申请日：2002-02-28

    申请人： Jung-Hwan Choi ,  Kwang-Sook Noh

    发明人： Jung-Hwan Choi ,  Kwang-Sook Noh

    IPC分类号： H03K522

    CPC分类号： H03K5/125

    摘要： Data input receivers reproduce data signals, and methods detect data signals in data input receivers. The invention receives an input data signal and two reference signals, which may be complementary. A first voltage difference between the input data signal and the first reference signal is amplified, and a second voltage difference between the input data signal and the second reference signal is amplified. The amplified first voltage difference and the amplified second voltage difference are received on the same pair of output terminals, which are then compared to generate the reproduced data signal.

    摘要翻译： 数据输入接收机再现数据信号，方法检测数据输入接收机中的数据信号。 本发明接收输入数据信号和两个参考信号，其可以是互补的。 放大输入数据信号和第一参考信号之间的第一电压差，并且放大输入数据信号和第二参考信号之间的第二电压差。 放大的第一电压差和放大的第二电压差被接收在同一对输出端上，然后进行比较以产生再现的数据信号。

    Semiconductor memory device having swap function for data output pads
    5.
    发明授权
    Semiconductor memory device having swap function for data output pads 有权
    半导体存储器件具有用于数据输出焊盘的交换功能

    公开(公告)号：US08331161B2

    公开(公告)日：2012-12-11

    申请号：US12662018

    申请日：2010-03-29

    申请人： Kwang-Sook Noh

    发明人： Kwang-Sook Noh

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1045 ,  G11C7/1051 ,  G11C2207/105

    摘要： A semiconductor memory device having a status register read function includes a plurality of data output pads electrically connected to corresponding package pin, and a swap controller connected between the plurality of data output pads and a plurality of output lines that output memory-related unique information in a specific operation mode. The swap controller controls a swap according to preset swap program information when a swap is needed to match the data output pads to the package pins.

    摘要翻译： 具有状态寄存器读取功能的半导体存储器件包括电连接到相应的封装引脚的多个数据输出焊盘和连接在多个数据输出焊盘之间的交换控制器和输出与存储器有关的唯一信息的多个输出线 具体操作模式。 交换控制器根据预置的交换程序信息控制交换，当需要进行交换以将数据输出焊盘与封装引脚匹配时。

    METHODS OF OPERATING DRAM DEVICES HAVING ADJUSTABLE INTERNAL REFRESH CYCLES THAT VARY IN RESPONSE TO ON-CHIP TEMPERATURE CHANGES
    6.
    发明申请
    METHODS OF OPERATING DRAM DEVICES HAVING ADJUSTABLE INTERNAL REFRESH CYCLES THAT VARY IN RESPONSE TO ON-CHIP TEMPERATURE CHANGES 有权
    具有可调节内部温度变化的可调节内部循环的DRAM器件的操作方法

    公开(公告)号：US20120224444A1

    公开(公告)日：2012-09-06

    申请号：US13471592

    申请日：2012-05-15

    申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

    发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

    IPC分类号： G11C7/22

    CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

    摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

    摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

    Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes
    7.
    发明授权
    Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes 有权
    操作具有可变内部刷新周期的DRAM器件的方法，其响应片上温度变化而变化

    公开(公告)号：US08675438B2

    公开(公告)日：2014-03-18

    申请号：US14017080

    申请日：2013-09-03

    申请人： Kwang Sook Noh ,  Young Hun Seo ,  Jong Hyun Choi

    发明人： Kwang Sook Noh ,  Young Hun Seo ,  Jong Hyun Choi

    IPC分类号： G11C7/00

    CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

    摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

    摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

    METHODS OF OPERATING DRAM DEVICES HAVING ADJUSTABLE INTERNAL REFRESH CYCLES THAT VARY IN RESPONSE TO ON-CHIP TEMPERATURE CHANGES
    8.
    发明申请
    METHODS OF OPERATING DRAM DEVICES HAVING ADJUSTABLE INTERNAL REFRESH CYCLES THAT VARY IN RESPONSE TO ON-CHIP TEMPERATURE CHANGES 有权
    具有可调节内部温度变化的可调节内部循环的DRAM器件的操作方法

    公开(公告)号：US20140016424A1

    公开(公告)日：2014-01-16

    申请号：US14017080

    申请日：2013-09-03

    申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

    发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

    IPC分类号： G11C11/402

    CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

    摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

    摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

    Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes
    9.
    发明授权
    Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes 有权
    操作具有可变内部刷新周期的DRAM器件的方法，其响应片上温度变化而变化

    公开(公告)号：US08218137B2

    公开(公告)日：2012-07-10

    申请号：US12941500

    申请日：2010-11-08

    申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

    发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

    IPC分类号： G11C7/00

    CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

    摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

    摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。

    Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes
    10.
    发明授权
    Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes 有权
    操作具有可变内部刷新周期的DRAM器件的方法，其响应片上温度变化而变化

    公开(公告)号：US08537633B2

    公开(公告)日：2013-09-17

    申请号：US13471592

    申请日：2012-05-15

    申请人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

    发明人： Kwang-Sook Noh ,  Young-Hun Seo ,  Jong-Hyun Choi

    IPC分类号： G11C7/00

    CPC分类号： G11C11/402 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40626 ,  G11C2211/4061

    摘要： An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

    摘要翻译： 集成电路存储器件包括刷新控制电路，该刷新控制电路产生具有相对于由存储器件接收的外部存储刷新命令信号的周期而改变的周期的内部存储器刷新命令信号。 内部存储器刷新命令的周期中的这种变化可以响应于检测到存储器件的温度变化。 特别地，刷新控制电路被配置为使得响应于检测到存储器件的温度降低而使内部存储器刷新命令信号的周期增加。