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18 条记录 (耗时 0.016 秒)

    DATA INPUT CIRCUIT
    2.
    发明申请
    DATA INPUT CIRCUIT 有权
    数据输入电路

    公开(公告)号：US20120026806A1

    公开(公告)日：2012-02-02

    申请号：US13051060

    申请日：2011-03-18

    申请人： Kyoung Hwan KWON

    发明人： Kyoung Hwan KWON

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/22 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093

    摘要： A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation.

    摘要翻译： 数据输入电路包括有效的选通信号产生电路和数据选通信号计数器。 有效选通信号产生电路被配置为去除产生的内部选通信号的脉冲并产生有效的选通信号。 脉冲可能在前导码期间产生。 数据选通信号计数器被配置为根据突发长度信息对有效的选通信号进行计数，并且在写入操作时产生用于对准数据的写入锁存信号。

    POWER-UP SIGNAL GENERATION CIRCUIT
    3.
    发明申请
    POWER-UP SIGNAL GENERATION CIRCUIT 有权
    上电信号发生电路

    公开(公告)号：US20110026335A1

    公开(公告)日：2011-02-03

    申请号：US12843883

    申请日：2010-07-27

    申请人： Kyoung Hwan KWON

    发明人： Kyoung Hwan KWON

    IPC分类号： G11C7/00 ,  H03L7/00

    CPC分类号： H03K17/145 ,  G11C7/04 ,  G11C7/20

    摘要： A power-up signal generation circuit includes a fixed level transition voltage generation unit, a variable level transition voltage generation unit, a comparison unit, and a selective output unit. The fixed level transition voltage generation unit is configured to generate a fixed level transition voltage changing at a constant level of an external voltage. The variable level transition voltage generation unit is configured to generate a variable level transition voltage changing at a level of an external voltage which varies depending on temperature. The comparison unit is configured to compare the level of the fixed level transition voltage with the level of the variable level transition voltage, and generate a selection signal. The selective output unit is configured to output the fixed level transition voltage or the variable level transition voltage as a power-up signal in response to the selection signal.

    摘要翻译： 上电信号发生电路包括固定电平转换电压产生单元，可变电平转换电压产生单元，比较单元和选择输出单元。 固定电平转换电压产生单元被配置为产生以外部电压的恒定电平改变的固定电平转换电压。 可变电平转换电压产生单元被配置为产生在根据温度变化的外部电压的电平上变化的可变电平转换电压。 比较单元被配置为将固定电平转换电压的电平与可变电平转换电压的电平进行比较，并产生选择信号。 选择输出单元被配置为响应于选择信号而输出固定电平转换电压或可变电平转换电压作为上电信号。

    System having bus architecture for improving CPU performance and method thereof
    7.
    发明申请
    System having bus architecture for improving CPU performance and method thereof 审中-公开
    具有用于提高CPU性能的总线架构的系统及其方法

    公开(公告)号：US20070186026A1

    公开(公告)日：2007-08-09

    申请号：US11583254

    申请日：2006-10-19

    申请人： Kyoung-Hwan Kwon

    发明人： Kyoung-Hwan Kwon

    IPC分类号： G06F13/36

    CPC分类号： G06F13/1605 ,  G06F13/4031

    摘要： A system and method for improving the performance of a central processing unit (CPU), in which the system includes a first master such as a CPU, a first local bus connected to a memory device, a bridge, and a main bus connected to a second master and a peripheral device. The bridge is connected among the first master, the memory device, and the main bus and functions as a wrapper and also serves to decode an address output from the first master, monitor a status of ownership of the main bus, and output a wait signal to the first master based on a decoding result and a monitoring result. Accordingly, even while the second master is accessing the peripheral device via the main bus, the first master can access the memory device via the first local bus. The memory device includes a memory core storing predetermined data and a controller having an arbitration function.

    摘要翻译： 一种用于提高中央处理单元（CPU）的性能的系统和方法，其中系统包括诸如CPU的第一主站，连接到存储设备的第一局部总线，桥接器和连接到CPU的主总线 第二主机和外围设备。 桥接器连接在第一主机，存储设备和主总线之间，并且用作包装机，并且还用于对从第一主机输出的地址进行解码，监视主总线的所有权状态，并输出等待信号 基于解码结果和监视结果到第一主机。 因此，即使当第二主机经由主总线访问外围设备时，第一主机可以经由第一本地总线访问存储器设备。 存储装置包括存储预定数据的存储器核心和具有仲裁功能的控制器。

    DATA INPUT CIRCUIT
    8.
    发明申请
    DATA INPUT CIRCUIT 有权
    数据输入电路

    公开(公告)号：US20120113728A1

    公开(公告)日：2012-05-10

    申请号：US13096669

    申请日：2011-04-28

    申请人： Kyoung Hwan KWON ,  Tae Jin KANG ,  Sang Kwon LEE

    发明人： Kyoung Hwan KWON ,  Tae Jin KANG ,  Sang Kwon LEE

    IPC分类号： G11C7/10 ,  G11C8/18

    CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222

    摘要： A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.

    摘要翻译： 数据输入电路包括时钟采样单元，最终时钟产生单元和写入锁存信号产生单元。 采样单元被配置为产生包括在写入等待时间之后产生的脉冲的移位信号，并且在从产生移位信号的脉冲的时间开始的脉冲串周期期间，通过对内部时钟进行采样来产生采样时钟。 最终时钟生成单元被配置为通过与采样时钟同步地锁存移位信号来产生电平信号，并且响应于突发信号从电平信号产生最终时钟。 写锁存信号生成单元被配置为通过锁存最终时钟来产生使能信号，并且响应于使能信号产生用于锁存和输出对准数据的写锁存信号。

    Micro Controller Unit System Including Flash Memory and Method of Accessing the Flash Memory By the Micro Controller Unit
    10.
    发明申请
    Micro Controller Unit System Including Flash Memory and Method of Accessing the Flash Memory By the Micro Controller Unit 审中-公开
    包括闪存的微控制器单元系统和微控制器单元访问闪存的方法

    公开(公告)号：US20080195805A1

    公开(公告)日：2008-08-14

    申请号：US11833024

    申请日：2007-08-02

    申请人： Kyoung Hwan Kwon

    发明人： Kyoung Hwan Kwon

    IPC分类号： G06F12/06 ,  G06F12/00

    CPC分类号： G06F12/0607 ,  G06F2212/2022

    摘要： A micro controller unit (MCU) system and a flash memory accessing method performed by the MCU system are provided. In the flash memory accessing method, when a first address, which is currently accessed, is inconsecutive to a second address, which is accessed next to the first address, an MCU that accesses a plurality of flash memory blocks using an interleaving technique performs an address operation cycle on the second address. At substantially the same time, one of the flash memory blocks that includes an address next to the first address stores the next address of the first address and data of the next address in one of a plurality of registers.

    摘要翻译： 提供由MCU系统执行的微控制器单元（MCU）系统和闪速存储器访问方法。 在闪速存储器访问方法中，当当前访问的第一地址与第一地址旁边被访问的第二地址不一致时，使用交织技术访问多个闪存块的MCU执行地址 操作周期在第二个地址。 在基本相同的时间，包括第一地址旁边的地址的闪存块之一存储第一地址的下一个地址和多个寄存器之一中的下一个地址的数据。