公开(公告)号：US20240222961A1

公开(公告)日：2024-07-04

申请号：US18526607

申请日：2023-12-01

Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.

Inventor： Jifeng Zhou ,  Tsung-Wen Mou

IPC: H02H9/04

CPC classification number: H02H9/041

Abstract: In one embodiment, an asymmetric bidirectional surge protection device is provided, including a crowbar device, and a clamping device, wherein the crowbar device is formed in a first area of a semiconductor die, and wherein the clamping device is formed in a second area of the semiconductor die, wherein the second area surrounds the first area.

公开(公告)号：US20240145348A1

公开(公告)日：2024-05-02

申请号：US18495831

申请日：2023-10-27

Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.

Inventor： Lucas Zhang ,  Chao Gao ,  Lei He

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/04

CPC classification number: H01L23/49513 ,  H01L23/041 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/73263

Abstract: A semiconductor device including a housing, a semiconductor chip disposed within the housing and having first and second metal electrodes, a first lead frame having a first end extending out of the housing and a second end terminating in a die pad, a top surface of the die pad including a cavity having a first quantity of solder disposed therein for electrically connecting the die pad to the first metal electrode, a second lead frame having a first end extending out of the housing and having a second end disposed adjacent the semiconductor chip, and a clip having a first end connected to the second of the lead frame and a second end extending over the semiconductor chip, a bottom surface of the second end of the clip including a recess having a second quantity of solder disposed therein for electrically connecting the clip to the second metal electrode.

公开(公告)号：US20230326838A1

公开(公告)日：2023-10-12

申请号：US18132490

申请日：2023-04-10

Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.

Inventor： Lucas Zhang ,  Charlie Cai ,  Jifeng Zhou

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L23/49503 ,  H01L23/49517 ,  H01L24/40 ,  H01L23/564 ,  H01L2224/40175

Abstract: A discrete power semiconductor package includes a semiconductor chip, a heatsink, a first lead, a second lead, and a clip. The heatsink is adjacent the semiconductor chip and draws heat away from the semiconductor chip. The clip binds the semiconductor chip to the heatsink and includes a chip linker, a first terminal, and a second terminal. The chip linker is atop the semiconductor chip. The first terminal connects to the first lead and the second terminal connects to the second lead.

公开(公告)号：US11139287B2

公开(公告)日：2021-10-05

申请号：US16304223

申请日：2016-05-23

Applicant: Littelfuse Semiconductor (WUXI) Co., Ltd.

Inventor： Chuanfang Chin ,  Kueir-Liang Lu ,  Lei Shi ,  Tsungwen Mou

IPC: H01L27/02 ,  H01L23/525 ,  H02H9/04 ,  H02H1/04 ,  H02H3/22

Abstract: A transient voltage suppression (TVS) device including a TVS diode having a first electrode and a second electrode, an insulating plate disposed on the first electrode, a first terminal lead connected to the insulating plate, a second terminal lead connected to the second electrode, and an thermal cutoff element connecting the first terminal lead to the first electrode, the thermal cutoff element configured to melt and break an electrical connection between the first terminal lead and the first electrode when a temperature of the TVS diode exceeds a predetermined safety temperature.

公开(公告)号：US20210175224A1

公开(公告)日：2021-06-10

申请号：US17111690

申请日：2020-12-04

Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.

Inventor： Jianfei ZENG ,  CAI Yingda

IPC: H01L27/02 ,  H01L29/866 ,  H01L29/66

Abstract: In one embodiment, an asymmetric TVS device may include a semiconductor substrate, comprising an inner region, the inner region having a first polarity, and a first surface region, disposed on a first surface of the semiconductor substrate, the first surface region comprising a second polarity, opposite the first polarity. The asymmetric TVS device may also include a second surface region, comprising the second polarity, and disposed on a second surface of the semiconductor substrate, opposite the first surface, wherein the first surface region comprises a first dopant concentration, and wherein the second surface region comprises a second dopant concentration, greater than the first dopant concentration.

公开(公告)号：US20240112994A1

公开(公告)日：2024-04-04

申请号：US18375343

申请日：2023-09-29

Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.

Inventor： Lucas Zhang ,  Chao Gao ,  Lei He

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/433

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L23/4334 ,  H01L23/49503 ,  H01L24/37 ,  H01L24/40 ,  H01L23/3121 ,  H01L2224/37012 ,  H01L2224/37147 ,  H01L2224/40245

Abstract: A discrete semiconductor packaging structure and associated methods thereof. The structure includes a housing, a chip assembly pad being encapsulated by the housing, where the chip assembly pad is configured for coupling to a semiconductor chip. The structure further includes one or more leads, at least partially encapsulated by the housing, a clip including one or more terminals and a chip linker, where the terminals being configured for coupling to one or more leads, and a heat dissipation block, where the chip linker being coupled between the semiconductor chip and the heat dissipation block. The heat dissipation block is configured for removing heat from the semiconductor chip during operation.

公开(公告)号：US20240096872A1

公开(公告)日：2024-03-21

申请号：US18235193

申请日：2023-08-17

Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.

Inventor： Jifeng Zhou ,  Glenda Zhang ,  Chao Gao

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L29/0646 ,  H01L29/66121 ,  H01L29/861

Abstract: A TVS device may include a substrate, comprising a polarity of a first type, a first dopant layer, disposed on a first main surface of the substrate, and comprising a polarity of a second type, wherein the first dopant layer forms a P/N junction with the substrate. The TVS device may further include a second dopant layer, disposed on a second main surface of the substrate, opposite the first main surface, the second layer comprising the polarity of the first type, and a patterned layer, disposed on the second main surface of the substrate, the patterned layer comprising the polarity of the second type, wherein the patterned layer is interspersed with the second layer.

公开(公告)号：US20240071878A1

公开(公告)日：2024-02-29

申请号：US18231861

申请日：2023-08-09

Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.

Inventor： Lei Shi ,  Jifeng Zhou

IPC: H01L23/495 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/49575 ,  H01L23/49555 ,  H01L25/074 ,  H01L25/50 ,  H01L23/3121 ,  H01L23/49513 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014

Abstract: A lead frame package includes a first semiconductor chip, a second semiconductor chip, and a first lead frame. The first semiconductor chip is connected to a die attachment pad using a first clip. The second semiconductor chip is connected to the die attachment pad using a second clip. The die attachment pad is sandwiched between the first semiconductor chip and the second semiconductor chip. The first lead frame is connected to the die attachment pad.

公开(公告)号：US20240047317A1

公开(公告)日：2024-02-08

申请号：US18227051

申请日：2023-07-27

Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.

Inventor： Lucas Zhang ,  Chao Gao ,  Glenda Zhang

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49562 ,  H01L23/49537 ,  H01L23/49513 ,  H01L23/3107 ,  H01L24/40 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/40175 ,  H01L2224/32245 ,  H01L2224/73263 ,  H01L2224/92246

Abstract: Provided herein are package structures including a first lead frame having a first pedestal and a first lead extending from the first pedestal. A first perimeter ridge defines a first recessed area in a first main side of the first pedestal, wherein a die pad is positioned within the first recessed area. The package structure may further include a chip layer having a first main side opposite a second main side, wherein the second main side is in abutment with the first perimeter ridge of the pedestal of the first lead frame. The package structure may further include a clip including a second pedestal and a lead connector extending from the second pedestal, wherein a second perimeter ridge defines a second recessed area in a second main side of the second pedestal, and wherein the second perimeter ridge is in abutment with the first main side of the chip layer.

公开(公告)号：US20220310821A1

公开(公告)日：2022-09-29

申请号：US17706008

申请日：2022-03-28

Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.

Inventor： Jianfei Zeng

IPC: H01L29/66

Abstract: A method of forming a semiconductor device may include providing a semiconductor substrate, the semiconductor substrate comprising an inner region of a first polarity, and a surface layer, disposed on the inner region, wherein the surface layer comprises a second polarity, opposite the first polarity. The method may further include removing a surface portion of the semiconductor substrate using a saw, wherein a trench region is formed within the semiconductor substrate, and cleaning the trench region using a chemical process, wherein at least one mesa structure is formed within the semiconductor substrate.