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公开(公告)号：US06171912B2
公开(公告)日：2001-01-09
申请号：US09196067
申请日：1998-11-19
申请人： Louis Praamsma
发明人： Louis Praamsma
IPC分类号： H01L21336
CPC分类号： H01L29/7835 , H01L21/28114 , H01L21/2815 , H01L29/1045 , H01L29/402 , H01L29/42316 , H01L29/42376 , H01L29/4925 , H01L29/66659 , H01L29/66871
摘要： The invention relates to a method of manufacturing a field effect transistor, in particular a discrete field effect transistor, comprising a source region (1) and a drain region (2) and, between said regions, a channel region (4) above which a gate region (3) is located. The gate region (3) is formed by applying an insulating layer (5) to the semiconductor body and providing this insulating layer with a stepped portion (6) in the thickness direction, whereafter a conductive layer (30) is applied to the surface of the semiconductor body (10), which layer is substantially removed again by etching, so that a part (3A) of the conductive layer (30), which part forms part of the gate region (3) and which lies against the stepped portion (6), remains intact. In a method in accordance with the invention, the source region (1) and the drain region (2) are formed before the insulating layer (5) is provided, and after the provision of the part (3A) of the gate region (3), which part is formed from the conductive layer (30), the surface of the semiconductor body (10) is made flat by applying a further insulating layer (7) next to the stepped portion (6). Such a method enables a T-shaped gate region (3) to be manufactured in a simple manner, said gate region comprising a very short vertical part (3A) of, for example, polycrystalline silicon and an overlying wider horizontal part of, for example, aluminium. Such a transistor has excellent high-frequency properties. In a preferred embodiment, the stepped portion (6) is formed by providing the insulating layer with a recess (8) whose side walls are situated above the source region (1) and the channel region (4). In a particularly simple variant, a “parasitic” gate region (32) is subsequently formed above the source region (1), which is not objectionable. The recess (8) can further be used in the formation of LDMOST whose source region (1) can be provided with an extension (1A).
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公开(公告)号：US20160190992A1
公开(公告)日：2016-06-30
申请号：US14635616
申请日：2015-03-02
CPC分类号： H03F1/0222 , H03F1/302 , H03F3/19 , H03F2200/165 , H03F2200/18 , H03F2200/294 , H03F2200/447 , H03F2200/451 , H03F2200/453 , H03F2200/456 , H03F2200/471
摘要： A bias circuit for a transistor amplifier, the bias circuit comprising a low-pass filter block, a reference transistor, a sum node, a reference current source, and a current difference block, wherein the low-pass filter block is configured to sense a DC bias voltage at a control terminal of the transistor amplifier and provide the DC bias voltage to a control terminal of the reference transistor; the reference transistor is configured to output a bias current in response to the DC bias voltage and provide the bias current to the sum node; the sum node is configured to receive a reference current from the reference current source and combine the reference current with the bias current from the reference transistor to provide a difference current; and the current difference block is configured to receive the difference current from the sum node and provide the difference current to the control terminal of the transistor amplifier.
摘要翻译： 一种用于晶体管放大器的偏置电路，所述偏置电路包括低通滤波器块，参考晶体管，和节点，参考电流源和电流差分块，其中所述低通滤波器块被配置为感测 DC偏置电压，并将DC偏置电压提供给参考晶体管的控制端; 参考晶体管被配置为响应于DC偏置电压输出偏置电流，并将偏置电流提供给和节点; 所述和节点被配置为从所述参考电流源接收参考电流，并且将所述参考电流与来自所述参考晶体管的所述偏置电流组合以提供差分电流; 并且电流差分块被配置为从和节点接收差分电流，并将差分电流提供给晶体管放大器的控制端子。
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公开(公告)号：US5719428A
公开(公告)日：1998-02-17
申请号：US656994
申请日：1996-05-24
CPC分类号： H01L27/0259
摘要： A semiconductor device with a semiconductor body (3) including a surface region (5) of a first conductivity type which adjoins a surface (4) and in which a field effect transistor (1) with insulated gate (6) is provided. The field effect transistor (1) has source and drain regions (7, 8, respectively) of the second, opposed conductivity type situated in the surface region (5), and a channel region (9) of the first conductivity type situated between the source and drain regions. A metal gate electrode (6) separated from the channel region (9) by an insulating layer (10) is provided over the channel region (9) and is provided with a protection device (2) against excessive voltages applied to the gate electrode (6). According to the invention, the surface (4) of the semiconductor body (3) is provided with a locally recessed field oxide (15), and the protection device (2) includes a lateral bipolar transistor with collector and emitter regions (16, 17, respectively) of the second conductivity type which are more strongly doped than the surface region (5) and which adjoin the surface (4) and the field oxide (15), and with a base region (18) of the first conductivity type which is more strongly doped than the surface region (5) and which lies below the field oxide (15), the collector region (16) being electrically connected to the gate electrode (6) and the emitter region (17) being electrically connected to the source region (7). It is achieved thereby that the field effect transistor (1) can switch high frequencies much more quickly.
摘要翻译： 一种具有半导体本体（3）的半导体器件，其包括邻接表面（4）的第一导电类型的表面区域（5），并且其中设置有具有绝缘栅极（6）的场效应晶体管（1）。 场效应晶体管（1）分别具有位于表面区域（5）中的第二相对导电类型的源极和漏极区域（7,8）和位于表面区域（5）之间的第一导电类型的沟道区域（9） 源极和漏极区域。 通过绝缘层（10）与通道区域（9）分离的金属栅电极（6）设置在通道区域（9）上，并且设置有保护装置（2），以防止施加到栅极电极 6）。 根据本发明，半导体主体（3）的表面（4）设置有局部凹陷的场氧化物（15），并且保护装置（2）包括具有集电极和发射极区域（16,17）的横向双极晶体管 （5）并且与表面（4）和场氧化物（15）相邻并且与第一导电类型的基极区域（18）分别比第二导电类型更强地掺杂并且与第一导电类型的基极区域 比表面区域（5）更强地掺杂，并且位于场氧化物（15）的下方，集电极区域（16）电连接到栅电极（6），并且发射极区域（17）电连接到 源区域（7）。 因此，场效应晶体管（1）可以更快地切换高频。
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公开(公告)号：US5528065A
公开(公告)日：1996-06-18
申请号：US457945
申请日：1995-06-01
CPC分类号： H01L29/0847 , H01L29/7831
摘要： A dual-gate insulated gate field effect device (1) such as a MOS tetrode has an active device area (3) in which adjacent source regions (5) are separated by and spaced apart from an intervening drain region (6) to define a respective conduction channel region (7) between each source and drain region (5 and 6). An insulated gate structure (10) has first insulated gate sections (11) forming an inner insulated gate (110) connected so as to surround each drain region 6 and second insulated gate sections (12) provided between the first insulated gate sections (11) and the source regions (5) and forming an outer insulated gate (120). Ends (11a,12a) of the insulated gate sections (11 and 12) extend onto the surrounding field oxide (4) to connect with respective first and gate conductors (13 and 14). Each drain region (6) is associated with an additional source region (50) spaced apart from the drain region (6) in a direction parallel to the width W of the conduction channel regions to define an additional conduction channel region. The second insulated gate sections (12) are connected to provide an area of insulated gate (12b) between each additional source region (50) and the associated drain region (6). This substantially eliminates leakage currents and enables the use of a design in which parasitic capacitances are reduced.
摘要翻译： 诸如MOS四极管的双栅极绝缘栅场效应器件（1）具有有源器件区域（3），其中相邻的源极区域（5）由中间的漏极区域（6）分开并与之隔开，以限定一个 每个源极和漏极区域（5和6）之间的各个导电沟道区域（7）。 绝缘栅极结构（10）具有形成内部绝缘栅极（110）的第一绝缘栅极部分（11），其围绕每个漏极区域6和设置在第一绝缘栅极部分（11）之间的第二绝缘栅极部分（12） 和源极区（5）并形成外部绝缘栅极（120）。 绝缘栅极部分（11和12）的端部（11a，12a）延伸到周围的场氧化物（4）上，以与相应的第一和栅极导体（13和14）连接。 每个漏极区域（6）与平行于导电沟道区域的宽度W的方向上与漏极区域（6）间隔开的附加源极区域（50）相关联，以限定附加的导电沟道区域。 第二绝缘栅极部分（12）被连接以在每个附加源极区域（50）和相关联的漏极区域（6）之间提供绝缘栅极（12b）的区域。 这实质上消除了泄漏电流，并且能够使用其中寄生电容减小的设计。
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公开(公告)号：US5216383A
公开(公告)日：1993-06-01
申请号：US872938
申请日：1992-04-23
摘要： A controllable amplifier circuit includes, successively, in a cascode arrangement between a power supply voltage and ground, a control transistor and a field effect amplifier transistor having a control input for applying a gain control signal thereto and a gate input for applying an input signal thereto, respectively, via which control transistor the field effect amplifier transistor supplies an output signal to a signal output of the controllable amplifier circuit. The control transistor varies the working point of the field effect amplifier transistor in the ohmic range in dependence upon the gain control signal, at least in a part of the control range of the gain control signal. The circuit can be used with a low power supply voltage because the controllable amplifier circuit includes a controllable bias circuit which is coupled to the gate input of the field effect amplifier transistor for applying a controllable bias voltage thereto. This voltage varies in the opposite direction to the gain control signal mainly in said part of the control range.
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公开(公告)号：US09548701B2
公开(公告)日：2017-01-17
申请号：US14635616
申请日：2015-03-02
CPC分类号： H03F1/0222 , H03F1/302 , H03F3/19 , H03F2200/165 , H03F2200/18 , H03F2200/294 , H03F2200/447 , H03F2200/451 , H03F2200/453 , H03F2200/456 , H03F2200/471
摘要： A bias circuit for a transistor amplifier, the bias circuit comprising a low-pass filter block, a reference transistor, a sum node, a reference current source, and a current difference block, wherein the low-pass filter block is configured to sense a DC bias voltage at a control terminal of the transistor amplifier and provide the DC bias voltage to a control terminal of the reference transistor; the reference transistor is configured to output a bias current in response to the DC bias voltage and provide the bias current to the sum node; the sum node is configured to receive a reference current from the reference current source and combine the reference current with the bias current from the reference transistor to provide a difference current; and the current difference block is configured to receive the difference current from the sum node and provide the difference current to the control terminal of the transistor amplifier.
摘要翻译： 一种用于晶体管放大器（Q1）的偏置电路，所述偏置电路包括低通滤波器块（1），参考晶体管（Q2），总和节点（14），参考电流源（4）和电流 差分块（5），其中所述低通滤波器块（1）被配置为感测所述晶体管放大器（Q1）的控制端的DC偏置电压，并将所述DC偏置电压提供给所述参考晶体管的控制端（ Q2）; 参考晶体管（Q2）被配置为响应于DC偏置电压输出偏置电流，并向和节点（14）提供偏置电流; 总和节点（14）被配置为从参考电流源（4）接收参考电流，并将参考电流与来自参考晶体管（Q2）的偏置电流组合以提供差分电流; 并且电流差分块（5）被配置为从和节点（14）接收差分电流，并将差动电流提供给晶体管放大器（Q1）的控制端子。
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7.发明授权Electrically-programmable semiconductor memories with buried injector region 失效具有埋入式注射器区域的电可编程半导体存储器
公开(公告)号：US5216269A
公开(公告)日：1993-06-01
申请号：US745992
申请日：1991-08-08
IPC分类号： H01L29/788
CPC分类号： H01L29/7884
摘要： Each memory cell of an electrically-programmable semiconductor memory has a field-effect transistor with a charge-storage region. Efficient and fast injection of hot carriers into the charge-storage region is achieved by vertical punch-through of a depletion layer to a buried injector region, by application of programming voltages to a control gate and to the surface of the punch-through region. Non-injected carriers are removed via at least the transistor drain during the programming. A well-defined punch-through region can be obtained with a higher-doped boundary region at at least one side of the punch-through region to restrict the lateral spread of the depletion layer(s) and prevent parasitic connections. This permits closer spacing of the injector region to other regions of the memory cell, e.g. source and drain regions, and the injector region may adjoin an inset insulating field pattern. A compact cell array layout can be formed with a common connection region for the injector regions of two adjacent cells and for either a source or drain region of four other adjacent cells. The control gate and an erase gate may both be coupled in the same manner to the charge-storage region, and the cell can be operated with complementary voltage levels for writing and erasing. A feed-back mechanism with the start of injection from the punch-through and injector regions can provide a well-defined charge level limit for the erasure.
摘要翻译： 电可编程半导体存储器的每个存储单元具有具有电荷存储区域的场效应晶体管。 通过将编程电压施加到控制栅极和穿通区域的表面，通过将耗尽层垂直穿透到埋入式注入器区域来实现热载流子进入电荷存储区域的高效和快速注入。 在编程期间，非注入载流子至少通过晶体管漏极去除。 可以在穿通区域的至少一侧具有较高掺杂的边界区域来获得明确的穿通区域，以限制耗尽层的横向扩展并防止寄生连接。 这允许注射器区域与存储器单元的其它区域的更近的间隔，例如， 源极和漏极区域，并且注入器区域可以邻接插入绝缘场图案。 紧凑的单元阵列布局可以形成有用于两个相邻单元的注入器区域和四个其它相邻单元的源极或漏极区域的公共连接区域。 控制栅极和擦除栅极都可以以相同的方式耦合到电荷存储区域，并且可以以互补的电压电平对单元进行操作以进行写入和擦除。 具有从穿通和注射器区域的注入开始的反馈机构可以为擦除提供明确定义的电荷水平限制。
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