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公开(公告)号：US20190356321A1
公开(公告)日：2019-11-21
申请号：US15981948
申请日：2018-05-17
发明人： Igal Kushnir , Hung-Ming Chien , Wei-Hong Chen , Theodoros Chalvatzis , Seunghwan Yoon , Chin-Ming Chien , Tirdad Sowlati , Moche Cohen , Kobi Sturkovich , Shaul Klein
摘要： A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.
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公开(公告)号：US10419069B2
公开(公告)日：2019-09-17
申请号：US15608419
申请日：2017-05-30
摘要： Methods and systems are provided for telephone line access with crosstalk mitigation. Electronic equipment located at a first location may include a plurality of first transceiver devices, with each first transceiver device configured for coupling to a respective one of a plurality of telephone lines bundled together in a same telephone cable, to connect to a respective one of a plurality of second transceiver devices at a second location. Each first transceiver device controls communication over the respective telephone line, with controlling including assigning separate time slots for uplink communication and downline communication; and coordinating communication with other ones of the plurality of first transceiver devices, with the coordinating including aligning use of the time slots. Each transceiver device may include a coupling circuitry to connect to the respective telephone line, an analog front end; and a controller that controls communications over the telephone line.
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公开(公告)号：US10419008B2
公开(公告)日：2019-09-17
申请号：US15470375
申请日：2017-03-27
IPC分类号： H03L7/099 , H03B1/00 , H03L1/02 , H03B5/12 , H03B5/08 , H03B5/04 , H03L7/087 , H03L7/113 , H03L7/18
摘要： Methods and systems are provided for calibrating voltage-controlled oscillators (VCOs). frequency control information, relating to output frequency of a VCO, which varies based on changes in operational conditions, may be determined. The frequency control information enables indicating the output frequency within a range of allowable values for control inputs and a range of expected values based on the operational conditions. For each control input setting, calibration control information for a calibration voltage associated with a control input, may be determined, based on the frequency control information, with respect to the operational conditions, to generate a constant output frequency. The operational conditions may be assessed, and a calibration voltage corresponding to the assessed operational conditions may be determined. The calibration voltage may be applied, and based on applying the calibration voltage, a tuning control input for tuning the constant output frequency may be determined and applied to the VCO.
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公开(公告)号：US10284207B2
公开(公告)日：2019-05-07
申请号：US15812221
申请日：2017-11-14
摘要： Methods and systems are provided for adaptively configuring voltage-controlled oscillator (VCO) arrays, such as to reduce mismatches among the VCOs. A plurality of voltage-controlled oscillators (VCOs), connected in parallel to a common control input, and with each VCO outputting an oscillating signal based on the common control input and an adjustment input, may be configured to reduce mismatches among the VCOs. The plurality of VCO may be configured by adjusting at least one operational parameter applicable to interconnection paths connecting outputs of the plurality of VCOs; measuring a mismatch between signals at the outputs of the plurality of VCOs with respect to a first signal parameter; and adjusting a first operational parameter applicable to one or more of the plurality of VCOs to reduce mismatch between signals at the outputs of the plurality of VCOs with respect to a first signal parameter.
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公开(公告)号：US10243601B2
公开(公告)日：2019-03-26
申请号：US15830177
申请日：2017-12-04
发明人： Ronen Shaked , Ilan Reingold , Eitan Tsur , Eran Ridel
摘要： A system and method for frequency reuse for wireless point-to-point backhaul. Frequency reuse is enabled through the cancellation of interfering signals generated by interference sources. In one embodiment, a conventional dish antenna is complemented with one or more additional auxiliary antennas (e.g., isotropic). The one or more additional auxiliary antennas enable cancellation of interfering signals whose direction of arrival (DOA) is off the dish antenna's bore-sight.
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公开(公告)号：US20190036744A1
公开(公告)日：2019-01-31
申请号：US16147288
申请日：2018-09-28
发明人： Nadav Fine , Evgeny Levitan , Eran Ridel , Ran Soffer , Uri Kanari , Nati Mizrahi
摘要： In the subject system, a receiver includes a feed forward circuit, a phase recovery circuit, and a feedback circuit. The feed forward circuit compensates for near reflections and provides an input to the phase recovery circuit and the feedback circuit. The phase recovery circuit performs phase recovery and provides phase recovery information to the feedback circuit. The feedback circuit adjusts and/or corrects a received symbol based at least in part on the received phase recovery information.
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公开(公告)号：US10122520B2
公开(公告)日：2018-11-06
申请号：US15834201
申请日：2017-12-07
发明人： Kobi Sturkovich
摘要： A microwave backhaul system having quadruple capacity. In one embodiment, an outdoor communication unit in a microwave backhaul system is provided, which includes a first and second dual channel processing modules that are each configured to process two transmission/reception channels. The outdoor communication unit also includes two transmitter modules that are each configured to upconvert two channels for transmission at vertical polarization and a horizontal polarization.
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公开(公告)号：US10097188B2
公开(公告)日：2018-10-09
申请号：US15830105
申请日：2017-12-04
IPC分类号： H03L7/00
摘要： A system and method for system, method and apparatus for phase hits and microphonics cancellation. In addition to a first RF synthesizer source, a device also includes a second stable reference signal source that operates at a lower frequency as compared to the RF synthesizer source. The second stable reference signal source is selected with good phase noise characteristics and can be used to correct phase error events.
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公开(公告)号：US20180191368A1
公开(公告)日：2018-07-05
申请号：US15896632
申请日：2018-02-14
发明人： William Michael LYE , John B. Groe
CPC分类号： H03M1/662 , H03F1/02 , H03F3/24 , H03M1/742 , H04B1/0014 , H04B1/0025 , H04B1/0475 , H04B2001/045
摘要： An Interleaved Radio Frequency Digital-to-Analog Converter (RF DAC) suitable for use in cellular base stations and optimized to give both a wide RF tuning range and a wide RF bandwidth is disclosed. The RF DAC uses two levels of interleaving, the first providing a direct conversion path from Base Band (BB) to RF, and the second providing a variable interleaving factor through the use of summation to optimize the output bandwidth as a function of the RF center frequency. Digital Interpolation, including an arbitrary sample rate conversion filter, allows the RF DAC to operate from a wide range of possible BB sample rates and the DAC sample rate is a fixed ratio of the RF center frequency. As a result, the spurious outputs from the RF DAC are in known locations that are relatively easy to filter out, minimizing the frequency planning tasks required for a complete RF system design.
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公开(公告)号：US20180091166A1
公开(公告)日：2018-03-29
申请号：US15830144
申请日：2017-12-04
CPC分类号： H03M1/1245 , H03K5/249 , H03M1/1023 , H03M1/204 , H03M1/365
摘要： A system and method for sampling an RF signal are described. The system comprises a plurality of capacitors, a plurality of resistors, and a sampling circuit. A first port of each capacitor of the plurality of capacitors is coupled to the RF signal. A first port of each resistor of the plurality of resistors is coupled to one of a plurality of reference levels. A second port of each resistor of the plurality of resistors is coupled to a second port of a corresponding capacitor of the plurality of capacitors. The sampling circuit produces a plurality of digital outputs by sampling the second port of each resistor of the plurality of resistors.
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