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1.发明申请公开(公告)号：US20210385310A1
公开(公告)日：2021-12-09
申请号：US17406966
申请日：2021-08-19
发明人： Steven Scott GORSHE , Winston Mok
IPC分类号： H04L29/08 , H04L12/861
摘要： A source node for rate adapting a constant bit rate client signal into a signal stream in a 64B/66B-block telecom signal communication link includes a GMP engine; a FIFO buffer coupled to receive a 64B/66B encoded client data stream; a clock rate measuring circuit; a source of 64B/66B path overhead blocks; a source of 64B/66B pad blocks; a source of 64B/66B idle blocks; a multiplexer; and a multiplexer controller. A control 64B/66B block is encoded into an ordered set block-designator and a count of data blocks to be sent in a next path signal frame is encoded into a plurality of path overhead 64B/66B data blocks. The multiplexer controller is responsive to a count of data blocks to be sent in a next path signal frame from a previous GMP window frame to selectively pass data to a data output so as to fill a GMP window frame.
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2.发明申请公开(公告)号：US20190213156A1
公开(公告)日：2019-07-11
申请号：US16197109
申请日：2018-11-20
发明人： Sanjay Goyal
CPC分类号： G06F13/385 , G06F11/3409 , G06F13/4022 , G06F13/4045 , G06F2213/0028 , H04L43/0817 , H04L43/0894
摘要： A system and method for controlling the performance of one or more target devices. A connection request for a target device of a plurality of target devices is received at a serial attached SCSI (SAS) Expander from an SAS initiator device, wherein a maximum performance availability value is associated with the target device. If the current performance availability value of the target device indicates that the target device does have availability to service the connection request, the connection request from the SAS initiator device is accepted and a connection is established between the SAS initiator device and the target device. Alternatively, if the current performance availability value of the target device indicates that the target device does not have availability to service the connection request, the connection request from the SAS initiator device is rejected and a connection is not established between the SAS initiator device and the target device. Traffic flow between the devices is measured and the current performance availability value of the target device is updated to control the performance of the target device.
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公开(公告)号：US10230552B1
公开(公告)日：2019-03-12
申请号：US16046885
申请日：2018-07-26
摘要： A system and method for decision feedback equalizer (DFE) tap adaptation. An input signal is received at a DFE of a receiver, wherein the input signal comprises a serial bit stream of encoded symbols. Data samples and error samples are taken from the input signal and the data samples and the error samples are aligned establish a plurality of pairs of data samples and error samples, wherein the data sample and error sample of each of the plurality of pairs of data samples and error samples are from locations in the serial bit stream of encoded symbols that are known to be uncorrelated with each other. The DFE tap weights are then adjusted based upon the plurality of pairs of data samples and error samples.
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公开(公告)号：US20180316592A1
公开(公告)日：2018-11-01
申请号：US15949096
申请日：2018-04-10
发明人： Lars ELLEGAARD
IPC分类号： H04L12/26
CPC分类号： H04L47/283 , H04L43/106 , H04L43/50 , H04L47/31
摘要： A setup test method for scheduled networks, the method constituted of: transmitting a frame to at least one network switch; responsive to the transmitted frame arriving at a first time gate of the at least one network switch, timestamping the transmitted frame with a first time stamp; responsive to the transmitted frame traversing a second time gate of the at least one network switch, additionally timestamping the transmitted frame with a second time stamp; reading the first time stamp; responsive to the read first time stamp, determining the time of arrival of the transmitted frame at the first time gate; reading the second time stamp; and responsive to the read first time stamp, determining the time of traversal of the transmitted frame through the second time gate.
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公开(公告)号：US20180107452A1
公开(公告)日：2018-04-19
申请号：US15784981
申请日：2017-10-16
发明人： Dan Stiurca
IPC分类号： G06F7/501 , H03K17/687 , G06F5/01 , H04L5/14
摘要： Various transmission systems may benefit from techniques to improve the quality of the transmission. For example, certain full duplex transmission systems may include a virtual hybrid coupler. A circuit can include a first feedback resistor. The circuit can also include a second feedback resistor coupled to the first feedback resistor. The circuit can further include a first set of M transistors coupled to the first feedback resistor. The circuit can additionally include a second set of N transistors coupled to the second feedback resistor and to the first set of M transistors. The circuit can be configured to cancel a transmitted signal at a receiver input based on a ratio of resistance values of the first feedback resistor and the second feedback resistor, and based on a ratio of M to N.
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公开(公告)号：US20180097475A1
公开(公告)日：2018-04-05
申请号：US15718460
申请日：2017-09-28
CPC分类号： H03B1/04 , H03B5/12 , H03B5/1215 , H03B27/00 , H03B2200/0076 , H03B2200/009 , H03B2202/04
摘要： The present disclosure relates to a reconfigurable multicore inductor capacitor (LC) oscillator comprising a plurality of oscillator cores. The oscillator may be configured at run-time, at manufacturing, or at production, which may allow for the tailoring of operating characteristics of the oscillator, such as phase noise, electromagnetic interference, or power consumption, for a specific application after production. The cores are coupled through an interconnect network to a common electrical signal output. A subset of the cores may be selectively enabled while the remainder of the cores is disabled. The ability to enable only a subset of the cores allows the total number of enabled cores to be reconfigurable. Furthermore, the direction in which oscillation current flows through the inductor of the cores may be configured. Reconfiguring the number of enabled cores and/or the oscillation current direction in the cores allow operating characteristics of the oscillator to be tailored after production.
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公开(公告)号：US10528324B2
公开(公告)日：2020-01-07
申请号：US15784981
申请日：2017-10-16
发明人： Dan Stiurca
IPC分类号： G06F7/501 , G06F5/01 , H03K17/687 , H04L5/14 , H04B1/16
摘要： Various transmission systems may benefit from techniques to improve the quality of the transmission. For example, certain full duplex transmission systems may include a virtual hybrid coupler. A circuit can include a first feedback resistor. The circuit can also include a second feedback resistor coupled to the first feedback resistor. The circuit can further include a first set of M transistors coupled to the first feedback resistor. The circuit can additionally include a second set of N transistors coupled to the second feedback resistor and to the first set of M transistors. The circuit can be configured to cancel a transmitted signal at a receiver input based on a ratio of resistance values of the first feedback resistor and the second feedback resistor, and based on a ratio of M to N.
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公开(公告)号：US10355823B2
公开(公告)日：2019-07-16
申请号：US16105917
申请日：2018-08-20
发明人： Steven Scott Gorshe
摘要： A system and method for block-code transcoding. An input signal is analyzed to determine if the input signal includes multiple control words, multiple data words and a single control word or only data words. If the input signal comprises multiple control words, the method includes, generating a control word location map and mapping the control codes and any data words to a block-code encoded transmission signal. If the input signal comprises a single control word and multiple data words, the method includes, generating a control word location address indicating a location of the single control word and mapping the control code and the multiple data words to a block-code encoded transmission signal. If the input signal comprises only data words, the method includes, mapping the data words sequentially into the block-code encoded transmission signal. Accordingly, the bandwidth efficiency of the transmission signal is improved by varying the encoding technique used dependent upon the contents of the input signal.
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公开(公告)号：US09866658B2
公开(公告)日：2018-01-09
申请号：US15297625
申请日：2016-10-19
发明人： Cheng Yi , Heng Liao , Calvin Leung
IPC分类号： H04L29/14 , H04L12/741 , H04L12/751 , H04L12/931 , H04L29/08
CPC分类号： H04L69/40 , H04L45/08 , H04L45/745 , H04L49/356 , H04L67/1097
摘要： SAS expanders are commonly used within a SAS network topology to allow multiple disk drives (targets) to connect to multiple host devices (initiators). A connection between an initiator and a target is setup inside an expander on the pathway between the initiator and the target. A source device sends a connection request message called an open address frame using in-band signaling. The expander processes the open address frame and forwards an modified open address frame to the next expander in the path or to the final destination device.
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公开(公告)号：US09860004B2
公开(公告)日：2018-01-02
申请号：US14503082
申请日：2014-09-30
IPC分类号： H04J3/06
CPC分类号： H04J3/0697 , H04J3/0667 , H04J3/0673
摘要： A transparent clock may be provided between edge nodes of a non-precision time protocol network, with an arrival time of a packet at an edge of the non-precision time protocol network carried in a reserved field of a packet.
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