利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

41 条记录 (耗时 0.016 秒)

    LIGHT-EMITTING DEVICE AND DISPLAY UNIT AND LIGHTING UNIT USING THE SAME
    3.
    发明申请
    LIGHT-EMITTING DEVICE AND DISPLAY UNIT AND LIGHTING UNIT USING THE SAME 审中-公开
    发光装置和显示单元及使用其的照明单元

    公开(公告)号：US20100309646A1

    公开(公告)日：2010-12-09

    申请号：US12440179

    申请日：2007-10-17

    申请人： Makoto Morikawa ,  Tetsushi Tamura ,  Kenji Ueda ,  Hiroyuki Imamura

    发明人： Makoto Morikawa ,  Tetsushi Tamura ,  Kenji Ueda ,  Hiroyuki Imamura

    IPC分类号： F21V9/16 ,  F21V7/00 ,  F21V7/06

    CPC分类号： F21S6/002 ,  F21K9/62 ,  F21K9/64 ,  F21K9/68 ,  F21S6/004 ,  F21S8/00 ,  F21V7/041 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A light-emitting device (1) includes a base (10), a light reflecting member (11) placed on the base (10), a case (12) surrounding the light reflecting member (11), and a plurality of light-emitting elements (13) arranged on the inner surface of the case (12). The light reflecting member (11) reflects light emitted from an emission source including the light-emitting elements (13) toward an opening (12a) of the case (12). In the light-emitting device (1), since a plurality of light-emitting elements (13) can be arranged three-dimensionally, the size of the light-emitting device can be reduced easily. Moreover, the light reflecting member (11) reflects light emitted from the emission source including the light-emitting elements (13) toward the opening (12a) of the case (12), so that the light-emitting device can have high brightness.

    摘要翻译： 发光装置（1）包括基座（10），放置在基座（10）上的光反射部件（11），围绕光反射部件（11）的壳体（12） 布置在壳体（12）的内表面上的发光元件（13）。 光反射部件（11）将包括发光元件（13）的发光源的光朝向壳体（12）的开口（12a）反射。 在发光装置（1）中，由于可以三维地配置多个发光元件（13），所以能够容易地减小发光装置的尺寸。 此外，光反射部件（11）将从包含发光元件（13）的发光源射出的光朝向壳体（12）的开口部（12a）反射，使得发光元件能够具有高亮度。

    METHOD OF CONTROLLING CONTACT LOAD IN ELECTRONIC COMPONENT MOUNTING APPARATUS
    4.
    发明申请
    METHOD OF CONTROLLING CONTACT LOAD IN ELECTRONIC COMPONENT MOUNTING APPARATUS 审中-公开
    控制电子元件安装装置中接触负载的方法

    公开(公告)号：US20090151149A1

    公开(公告)日：2009-06-18

    申请号：US12389542

    申请日：2009-02-20

    申请人： Shuichi HIRATA ,  Yasuharu UENO ,  Makoto MORIKAWA ,  Hiroyuki YOSHIDA ,  Noriaki YOSHIDA

    发明人： Shuichi HIRATA ,  Yasuharu UENO ,  Makoto MORIKAWA ,  Hiroyuki YOSHIDA ,  Noriaki YOSHIDA

    IPC分类号： G01R31/28

    CPC分类号： B23K3/087 ,  B23K37/047 ,  H01L2224/75502 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49137 ,  Y10T29/53187

    摘要： A method of controlling contact load in an apparatus for mounting electronic components on a substrate includes a head holding an electronic component being lowered at a first speed to a first position where the electronic component does not contact the substrate. The head is lowered at a second speed slower than the first speed from the first position until a predetermined target contact load is detected. The head is moved down by a small step for a predetermined distance at the second speed and a contact load is measured after moving the head down. The method includes determining whether a measured contact load has reached the predetermined target contact load. The moving and the measuring is sequentially repeated until the measured contact load reaches the predetermined target contact load. The predetermined distance is set to a first predetermined distance when moving the head down until the electronic component contacts the substrate. The predetermined distance is set to a second predetermined distance when moving the head down after the electronic component contacts the substrate and the second predetermined distance is smaller than the first predetermined distance.

    摘要翻译： 一种在将电子部件安装在基板上的装置中控制接触负荷的方法包括将电子部件以第一速度降低到电子部件不与基板接触的第一位置的头部。 头部以比第一速度慢的第二速度从第一位置降低到检测到预定的目标接触负载。 头部以第二速度向下移动一小段预定距离，并且在向下移动头部之后测量接触负载。 该方法包括确定所测量的接触负载是否达到预定的目标接触负载。 依次重复移动和测量直到所测量的接触负载达到预定的目标接触负载。 当向下移动头部直到电子部件接触基板时，预定距离被设定为第一预定距离。 在电子部件接触基板之后向下移动头部并且第二预定距离小于第一预定距离时，将预定距离设定为第二预定距离。

    Arithmetic processing apparatus
    7.
    发明授权
    Arithmetic processing apparatus 有权
    算术处理装置

    公开(公告)号：US07191201B2

    公开(公告)日：2007-03-13

    申请号：US10421125

    申请日：2003-08-04

    申请人： Makoto Morikawa ,  Atsushi Katsumata ,  Koji Kobayashi

    发明人： Makoto Morikawa ,  Atsushi Katsumata ,  Koji Kobayashi

    IPC分类号： G06F7/38 ,  G06F17/14

    CPC分类号： G06F9/3001 ,  G06F9/345 ,  G06F17/142

    摘要： An arithmetic processing apparatus includes a first data storage unit, two-dimensional arithmetic unit, and main control unit. The first data storage unit stores data to be processed. The two-dimensional arithmetic unit performs two-dimensional operation. The main control unit controls the two-dimensional arithmetic unit. The two-dimensional arithmetic unit includes an input address calculation unit which calculates the addresses of a set of input data necessary for a designated type of operation in the first data storage unit in accordance with an execution start instruction which designates the type of operation and a parameter from the main control unit, and an arithmetic execution unit which performs the designated type of operation for the set of input data which are stored at the calculated addresses in the first data storage unit.

    摘要翻译： 算术处理装置包括第一数据存储单元，二维运算单元和主控单元。 第一数据存储单元存储要处理的数据。 二维运算单元进行二维运算。 主控制单元控制二维运算单元。 二维算术单元包括输入地址计算单元，其根据指定操作类型的执行开始指令来计算第一数据存储单元中的指定类型的操作所需的一组输入数据的地址，以及 参数，以及算术执行单元，其对存储在第一数据存储单元中的计算的地址的输入数据集进行指定的操作类型。

    Verification method of logical circuit layout patterns
    8.
    发明授权
    Verification method of logical circuit layout patterns 失效
    逻辑电路布局模式的验证方法

    公开(公告)号：US5359534A

    公开(公告)日：1994-10-25

    申请号：US823966

    申请日：1992-01-22

    申请人： Hirokazu Fujiki ,  Makoto Morikawa

    发明人： Hirokazu Fujiki ,  Makoto Morikawa

    IPC分类号： H01L21/66 ,  G06F17/50 ,  G06F15/20 ,  G06F15/60

    CPC分类号： G06F17/5022

    摘要： A logical circuit layout pattern verification method. Verification of a logical circuit layout pattern is performed by: adding the parasitic capacitance of a layout pattern of a logical circuit to a load capacitance of logic gates, calculating an output value of the logical circuit based on the total capacitance, and verifying the layout pattern by comparing the output value and the expected output value calculated at initial design. In the calculation of the delay time of the logic gate, the delay time corresponding to discrete representative values of the load capacitance are first calculated, the functions describing the relationship between the load capacitance and the delay time are calculated using the delay time, and based on the function, the delay time corresponding to the load capacitance having continuous values is calculated. With the method, malfunctioning of the circuit caused by delay time is predictable.

    摘要翻译： 逻辑电路布局模式验证方法。 逻辑电路布局图案的验证是通过将逻辑电路的布局图案的寄生电容加到逻辑门的负载电容上，基于总电容计算逻辑电路的输出值，以及验证布局模式 通过比较初始设计时计算的输出值和预期输出值。 在计算逻辑门的延迟时间时，首先计算与负载电容的离散代表值相对应的延迟时间，描述负载电容与延迟时间之间的关系的函数使用延迟时间计算，并基于 在该功能上，计算与具有连续值的负载电容对应的延迟时间。 利用该方法，延迟时间引起的电路故障是可预测的。

    Apparatus for forming phosphor layer and method for forming phosphor layer using the apparatus
    10.
    发明授权
    Apparatus for forming phosphor layer and method for forming phosphor layer using the apparatus 失效
    用于形成荧光体层的设备和使用该设备形成荧光体层的方法

    公开(公告)号：US07992516B2

    公开(公告)日：2011-08-09

    申请号：US11722854

    申请日：2006-05-11

    申请人： Satoshi Shida ,  Hiroyuki Naito ,  Noriyasu Tanimoto ,  Yasuharu Ueno ,  Makoto Morikawa

    发明人： Satoshi Shida ,  Hiroyuki Naito ,  Noriyasu Tanimoto ,  Yasuharu Ueno ,  Makoto Morikawa

    IPC分类号： B05C5/02

    CPC分类号： H05B33/10 ,  H01L2224/48091 ,  H01L2924/00014

    摘要： A phosphor layer forming apparatus (1) in which a paste (21) containing a phosphor is discharged so as to cover each of a plurality of light-emitting elements (11) mounted on a substrate (10) includes the following: a discharge portion (12) for discharging the paste (21) in the form of droplets onto each of the light-emitting elements (11); a measurement portion (13) for measuring the thickness of individual phosphor layers that are formed of the paste (21) covering each of the light-emitting elements (11); and a discharge control portion (14) for controlling the amount of the paste (21) to be redischarged for each phosphor layer in accordance with the thickness of the individual phosphor layers measured by the measurement portion (13). This phosphor layer forming apparatus can reduce the manufacturing time.

    摘要翻译： 一种荧光体层形成装置（1），其中包含荧光体的浆料（21）被排出以覆盖安装在基板（10）上的多个发光元件（11）中的每一个，包括：排出部分 （12），用于以液滴的形式将糊状物（21）排出到每个发光元件（11）上; 测量部分（13），用于测量由覆盖每个发光元件（11）的浆料（21）形成的各个荧光体层的厚度; 以及放电控制部分（14），用于根据由测量部分（13）测量的各个荧光体层的厚度来控制针对每个荧光体层重新放电的糊状物（21）的量。 该荧光体层形成装置可以减少制造时间。