公开(公告)号：US20060166436A1

公开(公告)日：2006-07-27

申请号：US11043741

申请日：2005-01-26

申请人： Mark Korber

发明人： Mark Korber

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask layer further overlies a second mask layer overlying a second portion of the semiconductor substrate. The first mask layer overlying the first portion of the semiconductor substrate is patterned to define areas for removal of one or more layers of material interposed between the semiconductor substrate and the first mask layer. Portions of the one or more layers of material exposed by the patterned first mask layer are removed to define elements of the integrated circuit device overlying the first portion of the semiconductor substrate.

摘要翻译： 提供了形成集成电路器件的方法。 第一掩模层形成在半导体衬底的第一部分上。 第一掩模层还覆盖覆盖在半导体衬底的第二部分上的第二掩模层。 将覆盖在半导体衬底的第一部分上的第一掩模层图案化以限定插入在半导体衬底和第一掩模层之间的一层或多层材料的区域。 去除由图案化的第一掩模层暴露的一层或多层材料的部分，以限定覆盖半导体衬底的第一部分的集成电路器件的元件。

公开(公告)号：US08859382B2

公开(公告)日：2014-10-14

申请号：US13282355

申请日：2011-10-26

申请人： Noel Rocklein ,  D. V. Nirmal Ramaswamy ,  Dale W. Collins ,  Swapnil Lengade ,  Srividya Krishnamurthy ,  Mark Korber

发明人： Noel Rocklein ,  D. V. Nirmal Ramaswamy ,  Dale W. Collins ,  Swapnil Lengade ,  Srividya Krishnamurthy ,  Mark Korber

IPC分类号： H01L21/20 ,  H01L45/00

CPC分类号： H01L45/1641 ,  H01B1/08 ,  H01L21/283 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

摘要： Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. The degree of crystallinity within the metal oxide may be increased after the deposition of the metal oxide. A dielectric material may be formed over the metal oxide, and a second electrode may be formed over the dielectric material. The degree of crystallinity may be increased with a thermal treatment. The thermal treatment may be conducted before, during, and/or after formation of the dielectric material.

摘要翻译： 一些实施例包括形成存储器单元的方法。 金属氧化物可以沉积在第一电极上，沉积的金属氧化物具有相对低的结晶度。 在沉积金属氧化物之后，金属氧化物内的结晶度可以增加。 可以在金属氧化物上形成电介质材料，并且可以在电介质材料上形成第二电极。 可以通过热处理来提高结晶度。 热处理可以在形成介电材料之前，期间和/或之后进行。

公开(公告)号：US20130109147A1

公开(公告)日：2013-05-02

申请号：US13282355

申请日：2011-10-26

申请人： Noel Rocklein ,  D.V. Nirmal Ramaswamy ,  Dale W. Collins ,  Swapnil Lengade ,  Srividya Krishnamurthy ,  Mark Korber

发明人： Noel Rocklein ,  D.V. Nirmal Ramaswamy ,  Dale W. Collins ,  Swapnil Lengade ,  Srividya Krishnamurthy ,  Mark Korber

IPC分类号： H01L21/02 ,  C01B13/14 ,  C01F17/00 ,  C01G21/02 ,  C01G45/02 ,  C01G23/04 ,  C01G49/02 ,  C01D17/00 ,  H01L21/28 ,  C01F11/02

CPC分类号： H01L45/1641 ,  H01B1/08 ,  H01L21/283 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

摘要： Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. The degree of crystallinity within the metal oxide may be increased after the deposition of the metal oxide. A dielectric material may be formed over the metal oxide, and a second electrode may be formed over the dielectric material. The degree of crystallinity may be increased with a thermal treatment. The thermal treatment may be conducted before, during, and/or after formation of the dielectric material.

摘要翻译： 一些实施例包括形成存储器单元的方法。 金属氧化物可以沉积在第一电极上，沉积的金属氧化物具有相对低的结晶度。 在沉积金属氧化物之后，金属氧化物内的结晶度可以增加。 可以在金属氧化物上形成电介质材料，并且可以在电介质材料上形成第二电极。 可以通过热处理来提高结晶度。 热处理可以在形成介电材料之前，期间和/或之后进行。

公开(公告)号：US20060166437A1

公开(公告)日：2006-07-27

申请号：US11043838

申请日：2005-01-26

申请人： Mark Korber

发明人： Mark Korber

IPC分类号： H01L21/336

CPC分类号： H01L21/76229 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11531

摘要： A hard mask layer is formed and patterned overlying a semiconductor substrate of a semiconductor device. The patterned hard mask layer exposes two or more areas of the substrate for future isolation regions of the semiconductor device. Portions of the substrate are removed in the areas for future isolation regions, thereby forming two or more trenches. A second mask layer is formed overlying a first portion of the hard mask layer and at least one first trench, and a second portion of the hard mask layer and at least one second trench are left uncovered. Additional substrate material is removed from the at least one second trench so that the at least one second trench is deeper than the at least one first trench. The hard mask layer and the second mask are removed substantially concurrently.

摘要翻译： 在半导体器件的半导体衬底上形成并图案化硬掩模层。 图案化的硬掩模层暴露衬底的两个或更多个区域以用于半导体器件的未来隔离区域。 在用于将来的隔离区域的区域中去除衬底的一部分，从而形成两个或更多个沟槽。 覆盖硬掩模层的第一部分和至少一个第一沟槽，以及硬掩模层的第二部分和至少一个第二沟槽未覆盖的第二掩模层。 从所述至少一个第二沟槽移除附加的衬底材料，使得所述至少一个第二沟槽比所述至少一个第一沟槽更深。 基本上同时去除硬掩模层和第二掩模。

公开(公告)号：US20070259529A1

公开(公告)日：2007-11-08

申请号：US11827857

申请日：2007-07-13

申请人： Mark Korber

发明人： Mark Korber

IPC分类号： H01L21/311

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask layer further overlies a second mask layer overlying a second portion of the semiconductor substrate. The first mask layer overlying the first portion of the semiconductor substrate is patterned to define areas for removal of one or more layers of material interposed between the semiconductor substrate and the first mask layer. Portions of the one or more layers of material exposed by the patterned first mask layer are removed to define elements of the integrated circuit device overlying the first portion of the semiconductor substrate.