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公开(公告)号:US07893479B2
公开(公告)日:2011-02-22
申请号:US12538193
申请日:2009-08-10
申请人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
发明人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
IPC分类号: H01L29/108
CPC分类号: H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要: A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.
摘要翻译: 半导体结构。 硬掩模层位于半导体衬底的顶部衬底表面上。 硬掩模层包括硬掩模层开口,顶部衬底表面的一部分暴露于周围的环境中。 硬掩模层包括在顶部衬底表面上的衬垫氧化物层,衬垫氧化物层上的氮化物层,在氮化物层的顶部上的BSG(硼硅酸盐玻璃)层,以及顶部上的ARC(抗反射涂层) 的BSG层。 BSG层的BSG侧壁表面通过硬掩模层开口暴露于周围环境。
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公开(公告)号:US07573085B2
公开(公告)日:2009-08-11
申请号:US11458828
申请日:2006-07-20
申请人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
发明人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
IPC分类号: H01L27/108
CPC分类号: H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要: A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask layer opening comprises a top portion and a bottom portion, wherein the bottom portion is disposed between the top portion and the semiconductor substrate. The bottom portion has a greater lateral width than the top portion.
摘要翻译: 半导体结构。 该结构包括(a)半导体衬底; (b)半导体衬底上的硬掩模层; 和(c)在硬掩模层中开口的硬掩模层。 半导体衬底通过硬掩模层开口暴露于大气。 硬掩模层开口包括顶部和底部,其中底部设置在顶部和半导体衬底之间。 底部具有比顶部更宽的横向宽度。
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公开(公告)号:US20060275978A1
公开(公告)日:2006-12-07
申请号:US11458828
申请日:2006-07-20
申请人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey Maling , Lisa Ninomiya , Bruce Porth , Steven Shank , Jessica Trapasso
发明人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey Maling , Lisa Ninomiya , Bruce Porth , Steven Shank , Jessica Trapasso
IPC分类号: H01L21/8242 , H01L29/94 , H01L21/302
CPC分类号: H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要: A semiconductor structure. The structure includes (a) a semiconductor substrate; (b) a hard mask layer on top of the semiconductor substrate; and (c) a hard mask layer opening in the hard mask layer. The semiconductor substrate is exposed to the atmosphere through the hard mask layer opening. The hard mask layer opening comprises a top portion and a bottom portion, wherein the bottom portion is disposed between the top portion and the semiconductor substrate. The bottom portion has a greater lateral width than the top portion.
摘要翻译: 半导体结构。 该结构包括(a)半导体衬底; (b)半导体衬底上的硬掩模层; 和(c)在硬掩模层中开口的硬掩模层。 半导体衬底通过硬掩模层开口暴露于大气。 硬掩模层开口包括顶部和底部,其中底部设置在顶部和半导体衬底之间。 底部具有比顶部更宽的横向宽度。
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公开(公告)号:US07101806B2
公开(公告)日:2006-09-05
申请号:US10711953
申请日:2004-10-15
申请人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
发明人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
IPC分类号: H01L21/302
CPC分类号: H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要: A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.
摘要翻译: 一种用于蚀刻半导体衬底中的深沟槽的方法。 该方法包括以下步骤:(a)在半导体衬底的顶部上形成硬掩模层,(b)蚀刻硬掩模层中的硬掩模开口,以通过硬掩模层开口将半导体衬底暴露于大气中 其中蚀刻硬掩模开口的步骤包括蚀刻硬掩模开口的底部以使得硬掩模开口的底部的侧壁基本垂直的步骤,以及(c)蚀刻硬掩模开口的底部的深沟槽 基板通过硬掩模开口。
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公开(公告)号:US20060081556A1
公开(公告)日:2006-04-20
申请号:US10711953
申请日:2004-10-15
申请人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey Maling , Lisa Ninomiya , Bruce Porth , Steven Shank , Jessica Trapasso
发明人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey Maling , Lisa Ninomiya , Bruce Porth , Steven Shank , Jessica Trapasso
CPC分类号: H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要: A method for etching a deep trench in a semiconductor substrate. The method comprises the steps of (a) forming a hard mask layer on top of the semiconductor substrate, (b) etching a hard mask opening in the hard mask layer so as to expose the semiconductor substrate to the atmosphere through the hard mask layer opening, wherein the step of etching the hard mask opening includes the step of etching a bottom portion of the hard mask opening such that a side wall of the bottom portion of the hard mask opening is substantially vertical, and (c) etching a deep trench in the substrate via the hard mask opening.
摘要翻译: 一种用于蚀刻半导体衬底中的深沟槽的方法。 该方法包括以下步骤:(a)在半导体衬底的顶部上形成硬掩模层,(b)蚀刻硬掩模层中的硬掩模开口,以通过硬掩模层开口将半导体衬底暴露于大气中 其中蚀刻硬掩模开口的步骤包括蚀刻硬掩模开口的底部以使得硬掩模开口的底部的侧壁基本垂直的步骤,以及(c)蚀刻硬掩模开口的底部的深沟槽 基板通过硬掩模开口。
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公开(公告)号:US20090294926A1
公开(公告)日:2009-12-03
申请号:US12538193
申请日:2009-08-10
申请人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
发明人: June Cline , Dinh Dang , Mark Lagerquist , Jeffrey C. Maling , Lisa Y. Ninomiya , Bruce W. Porth , Steven M. Shank , Jessica A. Trapasso
IPC分类号: H01L29/06
CPC分类号: H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L29/66181 , Y10S438/952
摘要: A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.
摘要翻译: 半导体结构。 硬掩模层位于半导体衬底的顶部衬底表面上。 硬掩模层包括硬掩模层开口,顶部衬底表面的一部分暴露于周围的环境中。 硬掩模层包括在顶部衬底表面上的衬垫氧化物层,衬垫氧化物层上的氮化物层,在氮化物层的顶部上的BSG(硼硅酸盐玻璃)层,以及顶部上的ARC(抗反射涂层) 的BSG层。 BSG层的BSG侧壁表面通过硬掩模层开口暴露于周围环境。
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