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    Maintaining data connectivity for handoffs between compression-enabled and compression-disabled communication systems
    1.
    发明授权
    Maintaining data connectivity for handoffs between compression-enabled and compression-disabled communication systems 失效
    维护压缩和压缩禁用通信系统之间切换的数据连接

    公开(公告)号：US07668545B2

    公开(公告)日：2010-02-23

    申请号：US10956546

    申请日：2004-10-01

    申请人： Jeffrey Alan Dyck ,  Marcello Lioy ,  Paul McAllister

    发明人： Jeffrey Alan Dyck ,  Marcello Lioy ,  Paul McAllister

    IPC分类号： H04W36/00 ,  H04W4/00 ,  H04L12/56

    CPC分类号： H04W28/16 ,  H04W36/14 ,  H04W80/02

    摘要： Methods and apparatus are presented for enabling data connectivity when a handoff occurs between one communication network and another communication network, wherein the communication networks belong to different air interface standards. The mobile station triggers a Compression Control Protocol (CCP) request message to a tethered device if the mobile station determines that a new PDSN is not enabled to perform the CCP protocol. The tethered device then responds with a CCP request message with or without new negotiation parameters. The mobile station forwards the CCP request message to the new PDSN. Since the new PDSN is not enabled with CCP, the new PDSN responds with a CCP rejection message. The rejection message is passed from the mobile station back to the tethered device. The tethered device then sends uncompressed data packets to the PDSN.

    摘要翻译： 呈现当在一个通信网络和另一个通信网络之间发生切换时实现数据连接的方法和装置，其中通信网络属于不同的空中接口标准。 如果移动台确定新的PDSN未被启用以执行CCP协议，则移动台触发压缩控制协议（CCP）请求消息到系留设备。 该系留设备然后用或不带有新的协商参数的CCP请求消息进行响应。 移动台将CCP请求消息转发到新的PDSN。 由于新的PDSN未启用CCP，因此新PDSN以CCP拒绝消息作出响应。 拒绝消息从移动台传递回系留设备。 系留设备然后将未压缩的数据包发送到PDSN。

    Status bit controlled HDLC accelerator
    8.
    发明授权
    Status bit controlled HDLC accelerator 失效
    状态位控制HDLC加速器

    公开(公告)号：US5638370A

    公开(公告)日：1997-06-10

    申请号：US365356

    申请日：1994-12-28

    申请人： Mark Seconi ,  Paul McAllister ,  Glenn Lewis

    发明人： Mark Seconi ,  Paul McAllister ,  Glenn Lewis

    IPC分类号： H04L1/00 ,  H04L29/06 ,  H04L29/08 ,  H04T3/06

    CPC分类号： H04L1/0057 ,  H04L29/06 ,  H04L69/324

    摘要： A status bit controlled HDLC accelerator comprises a fully programmable CRC generation circuit, a partial data packet formatting/unformatting capability and a dual-mode register set. The HDLC accelerator includes a set of registers that can be written to and read from directly via a bus interface circuit. Moreover, these registers may be written to and read from at any time so that the state of the HDLC accelerator during a formatting or unformatting operation may be stored in mid-operation. The HDLC accelerator further includes a CRC generation circuit that can perform various checkword generation functions in response to a programmable CRC generator polynomial. In addition, programmable counters within the HDLC accelerator allow partial data packets to be processed which thereby enables formatting and unformatting data packets of all valid bit enumerations.

    摘要翻译： 状态位控制的HDLC加速器包括完全可编程的CRC生成电路，部分数据分组格式化/非格式化能力以及双模式寄存器组。 HDLC加速器包括一组可以通过总线接口电路直接写入和读取的寄存器。 此外，这些寄存器可以在任何时刻被写入和读取，使得格式化或非格式化操作期间的HDLC加速器的状态可以被存储在中间操作中。 HDLC加速器还包括CRC生成电路，其可以响应于可编程CRC生成多项式来执行各种复制词生成功能。 此外，HDLC加速器内的可编程计数器允许处理部分数据包，从而可以格式化和取消格式化所有有效位枚举的数据包。