摘要:
A shift register includes series-connection circuits to transmit a shift pulse. The series-connection circuits include a continuous stage group with continuous stages. Each stage of the continuous stage group includes a first output transistor, a first capacitor, an input gate, a first switching element, a second switching element, a third switching element, and a fourth switching element.
摘要:
Disclosed are a shift register and a display device which can suppress noise of output of each stage without causing an increase in circuit scale. In at least one example embodiment, each stage of the shift register includes a first output transistor, a second output transistor, a first capacitor, a second capacitor, an input gate, a first switching element, a second switching element, a third switching element, a fourth switching element, and a fifth switching element.
摘要:
Each stage of a shift register includes: a shift pulse input terminal; a shift pulse output terminal; first to fifth terminals; an input gate, first to fourth switching elements; a first output transistor, and a first circuit, connected between a first output terminal and the second input terminal, which forms a current path between the first output terminal and the second input terminal.
摘要:
Each stage (Xi) of a shift register includes a first output transistor (M5), a first capacitor (C1), an input gate (M1), a first switching element (M2), a second switching element (M3), a third switching element (M4), and a fourth switching element (M6).
摘要:
A multi-primary color display device is capable of handling an increased number of primary colors for color image display with a reduced number of external parts, with reduced increase in the amount of drive circuit and reduced increase in operating speed. An active matrix liquid crystal panel includes a display section constituted by pixel formation portions, each made of four sub pixel-formation portions which handle four primary colors. These four sub pixel-formation portions are arranged in a 2×2 matrix pattern. With such a pixel configuration, a source driver drives as many as M source lines, which is two times the number M of pixels arranged in a horizontal direction. A gate driver is formed on the liquid crystal panel integrally with pixel circuit in the display section, and drives as many as N gate lines, which is two times the number N of the pixels arranged in a vertical direction.
摘要:
In a liquid crystal display device in which one pixel is divided into a plurality of sub-pixels, power consumption is reduced. A liquid crystal display device in which a pixel formation portion forming one pixel includes a first sub-pixel portion and a second sub-pixel portion is provided with a charge sharing circuit (50) for short-circuiting a CS bus line (CSL1) provided for the first sub-pixel portion and a CS bus line (CSL2) provided for the second sub-pixel portion to each other based on a short-circuit control signal (CTL). A CS voltage generating circuit (40) generates CS signals (CS1 and CS2) whose potentials change every predetermined period. The charge sharing circuit (50) short-circuits the CS bus line (CSL1) and the CS bus line (CSL2) to each other at timing at which the potentials of the CS signals (CS1 and CS2) change, based on the short-circuit control signal (CTL).
摘要:
An auxiliary capacitor line driving circuit (5), provided in a surrounding region located around a display region (R1) in a liquid crystal display panel, generates auxiliary capacitor driving signals, and includes: first and second voltage trunk lines (VCS1, VCS2) which carry two different voltages, respectively; at least one control signal line (VCTRL1, VCTRL2) carrying one control signal; and a plurality of TFTs (T1, T2, T3, T4) each alternately supplying, to the respective auxiliary capacitor lines (CSn, CSn+1, and the like) in a given cycle, the two different voltages supplied to the auxiliary capacitor line driving circuit (5). Therefore, a liquid crystal display device employing multi-picture element drive method can be provided as a liquid crystal display device that achieves narrowing of a picture frame region as a non-display region and an external circuit board.
摘要:
A display device 10 according to the present invention includes a plurality of pixels 40 each including a plurality of sub pixels 42, a plurality of auxiliary capacitance lines 36 forming an auxiliary capacitance 56 with the sub pixels 42, and an auxiliary capacitance driver 34 configured to supply an auxiliary capacitance drive signal to the auxiliary capacitance lines 36 and to apply a voltage to the auxiliary capacitance. In the display device 10, the auxiliary capacitance driver 34 includes a plurality of connection terminals 64 each connected to each of the auxiliary capacitance lines 36.
摘要:
An auxiliary capacitor line driving circuit (5), provided in a surrounding region located around a display region (R1) in a liquid crystal display panel, generates auxiliary capacitor driving signals, and includes: first and second voltage trunk lines (VCS1, VCS2) which carry two different voltages, respectively; at least one control signal line (VCTRL1, VCTRL2) carrying one control signal; and a plurality of TFTs (T1, T2, T3, T4) each alternately supplying, to the respective auxiliary capacitor lines (CSn, CSn+1, and the like) in a given cycle, the two different voltages supplied to the auxiliary capacitor line driving circuit (5). Therefore, a liquid crystal display device employing multi-picture element drive method can be provided as a liquid crystal display device that achieves narrowing of a picture frame region as a non-display region and an external circuit board.
摘要:
A bistable circuit includes an output terminal that outputs a state signal, an output terminal that outputs an other-stage control signal, a first node of which a potential is controlled based on a set signal and a clear signal, a thin-film transistor that provides a potential of a second clock to the output terminal when a potential of the first node is at a high level, a thin-film transistor that provides a potential of a first clock to the output terminal when a potential of the first node is at a high level, and a thin-film transistor for changing a potential of the other-stage control signal to a low level based on a reset signal. The first clock is generated by a power source of a different system from the second clock, and has a smaller amplitude than that of the second clock.