摘要:
A liquid crystal display device of the present invention has a vertical scanning period in which the polarity of a display signal is positive and a vertical scanning period in which the polarity of a display signal is negative. When a pair of successive two vertical scanning periods is constituted by a first vertical scanning period and a second vertical scanning period, and when a target gradation level to be displayed in the first vertical scanning period is GL1, and a target gradation level to be displayed in the second vertical scanning period immediately after the first vertical scanning period is GL2, GL1 and GL2 being integers of 0 or more representing gradation levels, the liquid crystal display device includes a circuit (124) capable of supplying a display voltage corresponding to a gradation level to a pixel in the second vertical scanning period, the gradation level being expressed by GL2OD which satisfies a condition where |GL2OD-GL1| is larger than |GL2-GL1|, in the case where GL2 is different from GL1. The value of GL2OD when the polarity in the first vertical scanning period is positive and the polarity in the second vertical scanning period is negative is different from the value of GL2OD when the polarity in the first vertical scanning period is negative and the polarity in the second vertical scanning period is positive.
摘要:
Provided is a liquid crystal display device which displays each halftone by changing the luminance of pixels during a cycle (F1-F8) composed of a first term (F1-F2), a second term (F3-F4), a third term (F5-F6), and a fourth term (F7-F8). The liquid crystal display device includes: a type 1 pixel, which luminance level rises during the first term, rises or stays on hold during the second term, decays during the third term, and decays or stays on hold during the fourth term; a type 2 pixel, which luminance level decays during the first term, decays or stays on hold during the second term, rises during the third term, and rises or stays on hold during the fourth term; a type 3 pixel, which luminance level rises or stays on hold during the first term, decays during the second term, decays or stays on hold during the third term, and rises during the fourth term; a type 4 pixel, which luminance level decays or stays on hold during the first term, rises during the second term, rises or stays on hold during the third term, and decays during the fourth term to continuously display the same halftone.
摘要:
At least one embodiment of a liquid crystal display device including: pixels each of which includes a plurality of sub-pixels; and scanning signal lines provided in a display area, the scanning signal lines being divided into groups each of which includes a plurality of scanning signal lines, the groups being sequentially selected, the polarity POL of signal electric potentials being inverted when the selected group is changed from a preceding group to a succeeding group which is selected immediately after the preceding group, a plurality of (for example, two) dummy scanning periods being inserted between a horizontal scanning period corresponding to last horizontal scanning (scanning of G23) in the preceding group and a horizontal scanning period corresponding to first horizontal scanning (scanning of G2) in the succeeding group, and a scanning signal line (for example, G2) which belongs to a group selected after the preceding group being subjected to dummy scanning during each dummy scanning period so as to be made active for a predetermined period of time, and then deactivated. With the arrangement, it is possible to suppress horizontal-shaped unevenness that occurs in a case where block inversion driving is carried out in a multi-pixel mode liquid crystal display device.
摘要:
At least one embodiment of a liquid crystal display device including a display unit having scan signal lines divided into a plurality of groups which are successively selected. While the scan signal lines belonging to the selected group are successively scanned horizontally, signal potentials of the same polarity are successively supplied to a data signal line. The polarity of the signal potential is reversed between a preceding group and a subsequent group which are selected continuously. A plurality of dummy scan periods are inserted between the horizontal scan period corresponding to the last horizontal scan in the preceding group and the horizontal scan period corresponding to the first horizontal scan in the subsequent group. In each of the dummy scan periods, one of the scan signal lines which belong to the group selected after the preceding group is subjected to a dummy scan so that the scan signal line is maintained in an active state for a predetermined period and then deactivated so as to align the load state of a scan signal line drive circuit. This can reduce irregularities of the horizontal stripes when the data signal line is subjected to the block reverse drive.
摘要:
A gate driver creates a dummy insertion period in which the driver does not apply a gate on pulse to a scanning signal line immediately after the time of the inversion of a data signal. When a period from the time of the application of the gate on pulse to an odd numbered or even numbered scanning signal line to which the gate on pulse is applied previously to the time of the application of the gate on pulse to an even numbered or odd numbered scanning signal line to which the gate on pulse is applied later is set as an adjacent line writing time lag period for two scanning signal lines adjacent to each other, a CS control circuit allows the polarity of every CS signal to be reversed on the same cycle at least in the adjacent line writing time lag period.
摘要:
A liquid crystal display device includes a liquid crystal panel in which a plurality of pixels (A) are arranged. A storage capacitor (Cs) is provided in each pixel (A) of liquid crystal panel. The storage capacitor (Cs) is connected to a Cs bus line. The liquid crystal display device includes a plurality of Cs bus lines. The Cs bus line is connected to a stem line. The stem line transfers a driving signal to the storage capacitor (Cs) via the Cs bus line. The liquid crystal display device includes a bridge line, separate from the stem line, for connecting a plurality of Cs bus lines.
摘要:
In one embodiment of the present invention, a gate driver creates a dummy insertion period in which the driver does not apply a gate on pulse to a scanning signal line immediately after the time of the inversion of a data signal. When a period from the time of the application of the gate on pulse to an odd numbered or even numbered scanning signal line to which the gate on pulse is applied previously to the time of the application of the gate on pulse to an even numbered or odd numbered scanning signal line to which the gate on pulse is applied later is set as an adjacent line writing time lag period for two scanning signal lines adjacent to each other, a CS control circuit allows the polarity of every CS signal to be reversed on the same cycle at least in the adjacent line writing time lag period. This makes it possible to provide a liquid crystal display device capable of offering high quality display in which unevenness in the display is suppressed without being affected by the blunt waveform of the data signal and the blunt waveform of a retention volume signal at the time of the inversion.
摘要:
In a liquid crystal display device performing multi-picture element driving, gate OFF timing of a switching element connected between each sub picture element and a signal line is matched with phase timing when all the subsidiary capacity wires are at the same potential. This prevents the occurrence of uneven luminance appearing in a lateral streak.
摘要:
A liquid crystal display device of the present invention has a vertical scanning period in which the polarity of a display signal is positive and a vertical scanning period in which the polarity of a display signal is negative. When a pair of successive two vertical scanning periods is constituted by a first vertical scanning period and a second vertical scanning period, and when a target gradation level to be displayed in the first vertical scanning period is GL1, and a target gradation level to be displayed in the second vertical scanning period immediately after the first vertical scanning period is GL2, GL1 and GL2 being integers of 0 or more representing gradation levels, the liquid crystal display device includes a circuit (124) capable of supplying a display voltage corresponding to a gradation level to a pixel in the second vertical scanning period, the gradation level being expressed by GL2OD which satisfies a condition where |GL2OD-GL1| is larger than |GL2-GL1|, in the case where GL2 is different from GL1. The value of GL2OD when the polarity in the first vertical scanning period is positive and the polarity in the second vertical scanning period is negative is different from the value of GL2OD when the polarity in the first vertical scanning period is negative and the polarity in the second vertical scanning period is positive.
摘要:
The present invention is to provide a liquid crystal display device which hardly causes image sticking even when there is a difference in the pixel areas. The liquid crystal display device of the present invention includes a pair of substrates, and a liquid crystal layer sandwiched between the pair of substrates, and is configured such that a pixel is formed by picture elements of a plurality of colors. The liquid crystal display device of the present invention is featured in that one of the pair of substrates includes scanning lines, signal lines, and storage capacitor lines, a thin film transistor connected to each of the scanning line and the signal line, and a pixel electrode connected to the thin film transistor, in that the other of the pair of substrates includes an opposed electrode, in that the pixel electrode is arranged for each of the picture elements, and in that the pixel electrode having a larger area among the plurality of pixel electrodes arranged in one pixel is connected to the thin film transistor having a larger channel width among the plurality of the thin film transistors arranged in the one pixel.