公开(公告)号：US20050130785A1

公开(公告)日：2005-06-16

申请号：US10965002

申请日：2004-10-14

申请人： Masahiro Konda

发明人： Masahiro Konda

IPC分类号： F16H55/08 ,  F16H48/06 ,  F16H48/08

CPC分类号： F16H55/0886 ,  F16H48/08 ,  F16H55/0846 ,  F16H2048/082 ,  F16H2048/423 ,  F16H2048/426

摘要： The present invention is a bevel gear having a plurality of teeth (12) on an outside periphery thereof, each of both tooth flanks (13, 13) of each of the plurality of teeth (12) forming a crowning way with a bulge in a tooth trace direction, a generating line (P) of a standard pitch cone of each of the plurality of teeth (12) inclining with respect to an axial center (X, Y), wherein each of the tooth flanks (13) of the plurality of teeth (12) is formed into an arch shape, at least at a central portion thereof in the tooth trace direction.

摘要翻译： 本发明是一种锥齿轮，其在其外周上具有多个齿（12），所述多个齿（12）中的每一个的两个齿面（13,13）中的每一个形成具有凸起的隆起方式 所述多个齿（12）中的每一个的标准节圆锥体相对于轴向中心（X，Y）倾斜的生成线（P），其中，所述多个齿 的齿（12）至少在其沿磁迹方向的中心部分形成拱形。

公开(公告)号：US06691145B1

公开(公告)日：2004-02-10

申请号：US09615754

申请日：2000-07-13

申请人： Tadashi Shibata ,  Masahiro Konda ,  Tadahiro Ohmi

发明人： Tadashi Shibata ,  Masahiro Konda ,  Tadahiro Ohmi

IPC分类号： G06G700

CPC分类号： G11C11/5621 ,  G06G7/14 ,  G11C27/005 ,  H04N19/94

摘要： A computing circuit capable of computing an absolute difference with high-speed analog computation, a computing apparatus capable of computing the sum of absolute differences and a semiconductor computing circuit achievable with simple circuitry and suitable for use in such a computing circuit or apparatus. The computing circuit capable of computing the absolute difference includes a large input selection circuit 1 which outputs either a first signal or a second signal whichever is larger, a small input selection circuit 2 which outputs either the first and second signals whichever signal is smaller, and a subtraction circuit 3 which subtracts the output of the small input selection circuit 2 from the output of the large input selection circuit 1. The subtraction circuit 3 includes a capacitor 6, a first switch 4 provided between a first terminal of the capacitor 6 and the output of the large input selection circuit 1, a second switch 5 provided between the first terminal of the capacitor 6 and the output of the small input selection circuit 2, and a third switch 7 provided between a second terminal of the capacitor 6 and a terminal connected to a prescribed potential. The computing apparatus capable of computing the sum of absolute differences includes a plurality of such computing circuits, and computes the sum of the outputs of the computing circuits by using a summing circuit.

摘要翻译： 一种能够计算与高速模拟计算的绝对差异的计算电路，能够计算绝对差的和的计算装置以及适用于这种计算电路或装置的简单电路可实现的半导体计算电路。 能够计算绝对差的计算电路包括大输入选择电路1，其输出第一信号或第二信号（较大者），小输入选择电路2，其输出第一信号和第二信号，其中较小的信号;以及 减法电路3，其从大输入选择电路1的输出中减去小输入选择电路2的输出。减法电路3包括电容器6，设置在电容器6的第一端和第一开关4之间的第一开关4， 大输入选择电路1的输出，设置在电容器6的第一端子和小输入选择电路2的输出端之间的第二开关5以及设置在电容器6的第二端子与端子之间的第三开关7 连接到规定的电位。 能够计算绝对差的和的计算装置包括多个这样的计算电路，并且通过使用求和电路来计算计算电路的输出之和。

公开(公告)号：US5923205A

公开(公告)日：1999-07-13

申请号：US930372

申请日：1997-11-07

申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Masahiro Konda

发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Masahiro Konda

IPC分类号： G06G7/26 ,  G06G7/42

CPC分类号： G06G7/26

摘要： A semiconductor arithemetic circuit which performs calculation of an analog vector with a high accuracy at a high speed. A semiconductor arithemetic circuit having a plurality of MOS type transistors, wherein the source electrodes are connected to one another, the gate electrodes of the MOS type transistors are connected to a signal line having a prescribed potential via switching elements, and at least one input electrode is capacitively coupled with the gate electrodes; wherein circuitry is provided for applying first and second input voltages, respectively, to the input electrodes of at least one pair of first and second MOS type transistors among the plurality of MOS type transistors, and for equalizing potentials of the gate electrodes to the potential of the signal line by allowing the switching elements to conduct, and further circuitry means is provided for inputting the second and first input voltages into, respectively, the input electrodes of the first and second MOS type transistors after placing said gate electrodes in an electrically floating state by turning the switching elements off.

摘要翻译： PCT No.PCT / JP96 / 00882 Sec。 371日期：1997年11月7日 102（e）日期1997年11月7日PCT 1996年4月1日PCT PCT。 WO96 / 30853 PCT出版物 日期：1996年10月3日一种以高速度高精度地进行模拟矢量的计算的半导体仿真电路。 一种具有多个MOS型晶体管的半导体仿真电路，其中源极彼此连接，MOS型晶体管的栅电极通过开关元件连接到具有规定电位的信号线，并且至少一个输入电极 与栅电极电容耦合; 其中提供电路，用于将多个MOS型晶体管中的至少一对第一和第二MOS型晶体管的输入电极分别施加第一和第二输入电压，并将栅电极的电位与 信号线通过允许开关元件导通，并且还提供另外的电路装置，用于在将所述栅电极置于电浮动状态之后将第二和第一输入电压分别输入到第一和第二MOS型晶体管的输入电极中 通过关闭开关元件。

公开(公告)号：US20050163389A1

公开(公告)日：2005-07-28

申请号：US10507378

申请日：2002-09-19

申请人： Tadahiro Ohmi ,  Yukihiko Yokoyama ,  Masahiro Konda ,  Takahiro Nakayama

发明人： Tadahiro Ohmi ,  Yukihiko Yokoyama ,  Masahiro Konda ,  Takahiro Nakayama

IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/28 ,  H04N7/46 ,  G06K9/36

CPC分类号： G06T9/008 ,  H04N19/103 ,  H04N19/13 ,  H04N19/147 ,  H04N19/15 ,  H04N19/172 ,  H04N19/192 ,  H04N19/59 ,  H04N19/90 ,  H04N19/91 ,  H04N19/94 ,  H04N19/99

摘要： Input image data inputted in an image block of m pixels×n pixels is changed in the size of the image block; image data of the image block changed in size is subjected to compression processing; compressed image data obtained by the compression processing is subjected to expansion processing to generate restored image data in the m-pixel×n-pixel image block; and whether or not the size of the image block is further changed is judged based on the strength of the correlation between the restored image data and the input image data. The compression processing is performed on the image data while change in size of the image block is repeated until the correlation between the restored image data and the input image data is strong, thereby making it possible to perform compression processing on the image data of the input image at a high compression ratio while maintaining the image quality of the restored image.

摘要翻译： 在m像素×n像素的图像块中输入的输入图像数据在图像块的大小上改变; 尺寸变化的图像块的图像数据进行压缩处理; 对通过压缩处理获得的压缩图像数据进行扩展处理，以生成m像素像素图像块中的恢复图像数据; 并且基于恢复的图像数据和输入图像数据之间的相关强度来判断图像块的尺寸是否进一步改变。 对图像数据执行压缩处理，同时重复图像块的尺寸的改变直到恢复的图像数据和输入图像数据之间的相关性变强，从而可以对输入的图像数据进行压缩处理 在高压缩比下保持图像的图像质量。

公开(公告)号：US6115725A

公开(公告)日：2000-09-05

申请号：US14644

申请日：1998-01-28

申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Akira Nataka ,  Tatsuo Morimoto ,  Masahiro Konda

发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Akira Nataka ,  Tatsuo Morimoto ,  Masahiro Konda

IPC分类号： G06T9/00 ,  H03M7/30 ,  G06F7/00 ,  H04N7/12

CPC分类号： H03M7/3082 ,  G06T9/008 ,  H04N19/94

摘要： The real time compression of moving images employing vector quantization is realized using simple hardware and with an optimal compression ratio with respect to the communication line capacity employed. In the operating system, which is provided with a first mechanism (202), comprising a plurality of groups of numerical values, a second mechanism (201), a first circuit (206), a second circuit (206), and a third circuit (210), the second circuit comprises a plurality of fourth circuits divided into two or more groups (210-213, 219, and 301), the fourth circuits have a plurality of input terminals and at least one output terminal, and a mechanism is provided having a structure wherein various signals expressing degrees of similarity are inputted into the plurality of input terminals, only that signal having the largest degree of similarity among the variety of signals expressing degrees of similarity which are inputted is outputted from the output terminal, and the output signal of a predetermined first group among the two or more groups is inputted into an input terminal of a second group, whereby only one first vector having the largest degree of similarity is selected.

摘要翻译： 使用矢量量化的运动图像的实时压缩是使用简单的硬件和相对于所采用的通信线路容量的最佳压缩比来实现的。 在具有第一机构（202）的操作系统中，包括多组数值，第二机构（201），第一电路（206），第二电路（206）和第三电路 （210），所述第二电路包括分成两组或更多组（210-213,219和301）的多个第四电路，所述第四电路具有多个输入端子和至少一个输出端子，并且机构是 具有这样的结构，其中表示相似度的各种信号被输入到多个输入端，只有表示输入的相似度的各种信号之间具有最大相似程度的信号从输出端输出， 将两个以上组中的预定第一组的输出信号输入到第二组的输入端，由此仅选择具有最大相似度的一个第一矢量。

公开(公告)号：US06493263B1

公开(公告)日：2002-12-10

申请号：US09615755

申请日：2000-07-13

申请人： Tadashi Shibata ,  Masahiro Konda ,  Tadahiro Ohmi

发明人： Tadashi Shibata ,  Masahiro Konda ,  Tadahiro Ohmi

IPC分类号： G11C1604

CPC分类号： G06G7/14

摘要： Disclosed is a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed to compute an absolute-value voltage representing the difference between a first signal voltage and a second signal voltage. The semiconductor computing circuit comprises: a first MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate; a second MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate, and whose source electrode is connected to the source electrode of the first MOS transistor; a write circuit which, with a prescribed voltage applied to the control gates of the first and second MOS transistors, sets the potential at the floating gate of the first MOS transistor to a value equal to the first signal voltage and also sets the potential at the floating gate of the second MOS transistor equal to a value obtained by subtracting the first signal voltage from the prescribed voltage; and a difference voltage computing circuit for computing a voltage representing a value obtained by subtracting the second signal voltage from the prescribed voltage, and wherein: after setting the first and second MOS transistors by the write circuit, when the output voltage of the difference voltage computing circuit is applied to the control gate of the first MOS transistor while at the same time applying the second signal voltage to the control gate of the second MOS transistor, the absolute-value voltage representing the difference between the first signal voltage and the second signal voltage is output.

摘要翻译： 公开了一种可以用简单电路实现的半导体计算电路，能够高速执行模拟计算，以计算表示第一信号电压和第二信号电压之差的绝对值电压。 半导体计算电路包括：第一MOS晶体管，具有浮动栅极和与浮动栅极电容耦合的控制栅极; 具有浮置栅极和与栅极电容耦合的控制栅极的第二MOS晶体管，其源极连接到第一MOS晶体管的源极; 写入电路，其中施加到第一和第二MOS晶体管的控制栅极的规定电压将第一MOS晶体管的浮置栅极处的电位设置为等于第一信号电压的值，并且还将电位设置在 第二MOS晶体管的浮置栅极等于通过从规定电压减去第一信号电压而获得的值; 以及差分电压计算电路，用于计算表示通过从规定电压减去第二信号电压而获得的值的电压，并且其中：在通过写入电路设置第一和第二MOS晶体管之后，当差分电压计算的输出电压 电路施加到第一MOS晶体管的控制栅极，同时将第二信号电压施加到第二MOS晶体管的控制栅极，绝对值电压表示第一信号电压和第二信号电压之间的差 被输出。