公开(公告)号：US6115725A

公开(公告)日：2000-09-05

申请号：US14644

申请日：1998-01-28

申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Akira Nataka ,  Tatsuo Morimoto ,  Masahiro Konda

发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Akira Nataka ,  Tatsuo Morimoto ,  Masahiro Konda

IPC分类号： G06T9/00 ,  H03M7/30 ,  G06F7/00 ,  H04N7/12

CPC分类号： H03M7/3082 ,  G06T9/008 ,  H04N19/94

摘要： The real time compression of moving images employing vector quantization is realized using simple hardware and with an optimal compression ratio with respect to the communication line capacity employed. In the operating system, which is provided with a first mechanism (202), comprising a plurality of groups of numerical values, a second mechanism (201), a first circuit (206), a second circuit (206), and a third circuit (210), the second circuit comprises a plurality of fourth circuits divided into two or more groups (210-213, 219, and 301), the fourth circuits have a plurality of input terminals and at least one output terminal, and a mechanism is provided having a structure wherein various signals expressing degrees of similarity are inputted into the plurality of input terminals, only that signal having the largest degree of similarity among the variety of signals expressing degrees of similarity which are inputted is outputted from the output terminal, and the output signal of a predetermined first group among the two or more groups is inputted into an input terminal of a second group, whereby only one first vector having the largest degree of similarity is selected.

摘要翻译： 使用矢量量化的运动图像的实时压缩是使用简单的硬件和相对于所采用的通信线路容量的最佳压缩比来实现的。 在具有第一机构（202）的操作系统中，包括多组数值，第二机构（201），第一电路（206），第二电路（206）和第三电路 （210），所述第二电路包括分成两组或更多组（210-213,219和301）的多个第四电路，所述第四电路具有多个输入端子和至少一个输出端子，并且机构是 具有这样的结构，其中表示相似度的各种信号被输入到多个输入端，只有表示输入的相似度的各种信号之间具有最大相似程度的信号从输出端输出， 将两个以上组中的预定第一组的输出信号输入到第二组的输入端，由此仅选择具有最大相似度的一个第一矢量。

公开(公告)号：US06691145B1

公开(公告)日：2004-02-10

申请号：US09615754

申请日：2000-07-13

申请人： Tadashi Shibata ,  Masahiro Konda ,  Tadahiro Ohmi

发明人： Tadashi Shibata ,  Masahiro Konda ,  Tadahiro Ohmi

IPC分类号： G06G700

CPC分类号： G11C11/5621 ,  G06G7/14 ,  G11C27/005 ,  H04N19/94

摘要： A computing circuit capable of computing an absolute difference with high-speed analog computation, a computing apparatus capable of computing the sum of absolute differences and a semiconductor computing circuit achievable with simple circuitry and suitable for use in such a computing circuit or apparatus. The computing circuit capable of computing the absolute difference includes a large input selection circuit 1 which outputs either a first signal or a second signal whichever is larger, a small input selection circuit 2 which outputs either the first and second signals whichever signal is smaller, and a subtraction circuit 3 which subtracts the output of the small input selection circuit 2 from the output of the large input selection circuit 1. The subtraction circuit 3 includes a capacitor 6, a first switch 4 provided between a first terminal of the capacitor 6 and the output of the large input selection circuit 1, a second switch 5 provided between the first terminal of the capacitor 6 and the output of the small input selection circuit 2, and a third switch 7 provided between a second terminal of the capacitor 6 and a terminal connected to a prescribed potential. The computing apparatus capable of computing the sum of absolute differences includes a plurality of such computing circuits, and computes the sum of the outputs of the computing circuits by using a summing circuit.

摘要翻译： 一种能够计算与高速模拟计算的绝对差异的计算电路，能够计算绝对差的和的计算装置以及适用于这种计算电路或装置的简单电路可实现的半导体计算电路。 能够计算绝对差的计算电路包括大输入选择电路1，其输出第一信号或第二信号（较大者），小输入选择电路2，其输出第一信号和第二信号，其中较小的信号;以及 减法电路3，其从大输入选择电路1的输出中减去小输入选择电路2的输出。减法电路3包括电容器6，设置在电容器6的第一端和第一开关4之间的第一开关4， 大输入选择电路1的输出，设置在电容器6的第一端子和小输入选择电路2的输出端之间的第二开关5以及设置在电容器6的第二端子与端子之间的第三开关7 连接到规定的电位。 能够计算绝对差的和的计算装置包括多个这样的计算电路，并且通过使用求和电路来计算计算电路的输出之和。

公开(公告)号：US5923205A

公开(公告)日：1999-07-13

申请号：US930372

申请日：1997-11-07

申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Masahiro Konda

发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Masahiro Konda

IPC分类号： G06G7/26 ,  G06G7/42

CPC分类号： G06G7/26

摘要： A semiconductor arithemetic circuit which performs calculation of an analog vector with a high accuracy at a high speed. A semiconductor arithemetic circuit having a plurality of MOS type transistors, wherein the source electrodes are connected to one another, the gate electrodes of the MOS type transistors are connected to a signal line having a prescribed potential via switching elements, and at least one input electrode is capacitively coupled with the gate electrodes; wherein circuitry is provided for applying first and second input voltages, respectively, to the input electrodes of at least one pair of first and second MOS type transistors among the plurality of MOS type transistors, and for equalizing potentials of the gate electrodes to the potential of the signal line by allowing the switching elements to conduct, and further circuitry means is provided for inputting the second and first input voltages into, respectively, the input electrodes of the first and second MOS type transistors after placing said gate electrodes in an electrically floating state by turning the switching elements off.

摘要翻译： PCT No.PCT / JP96 / 00882 Sec。 371日期：1997年11月7日 102（e）日期1997年11月7日PCT 1996年4月1日PCT PCT。 WO96 / 30853 PCT出版物 日期：1996年10月3日一种以高速度高精度地进行模拟矢量的计算的半导体仿真电路。 一种具有多个MOS型晶体管的半导体仿真电路，其中源极彼此连接，MOS型晶体管的栅电极通过开关元件连接到具有规定电位的信号线，并且至少一个输入电极 与栅电极电容耦合; 其中提供电路，用于将多个MOS型晶体管中的至少一对第一和第二MOS型晶体管的输入电极分别施加第一和第二输入电压，并将栅电极的电位与 信号线通过允许开关元件导通，并且还提供另外的电路装置，用于在将所述栅电极置于电浮动状态之后将第二和第一输入电压分别输入到第一和第二MOS型晶体管的输入电极中 通过关闭开关元件。

公开(公告)号：US06493263B1

公开(公告)日：2002-12-10

申请号：US09615755

申请日：2000-07-13

申请人： Tadashi Shibata ,  Masahiro Konda ,  Tadahiro Ohmi

发明人： Tadashi Shibata ,  Masahiro Konda ,  Tadahiro Ohmi

IPC分类号： G11C1604

CPC分类号： G06G7/14

摘要： Disclosed is a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed to compute an absolute-value voltage representing the difference between a first signal voltage and a second signal voltage. The semiconductor computing circuit comprises: a first MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate; a second MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate, and whose source electrode is connected to the source electrode of the first MOS transistor; a write circuit which, with a prescribed voltage applied to the control gates of the first and second MOS transistors, sets the potential at the floating gate of the first MOS transistor to a value equal to the first signal voltage and also sets the potential at the floating gate of the second MOS transistor equal to a value obtained by subtracting the first signal voltage from the prescribed voltage; and a difference voltage computing circuit for computing a voltage representing a value obtained by subtracting the second signal voltage from the prescribed voltage, and wherein: after setting the first and second MOS transistors by the write circuit, when the output voltage of the difference voltage computing circuit is applied to the control gate of the first MOS transistor while at the same time applying the second signal voltage to the control gate of the second MOS transistor, the absolute-value voltage representing the difference between the first signal voltage and the second signal voltage is output.

摘要翻译： 公开了一种可以用简单电路实现的半导体计算电路，能够高速执行模拟计算，以计算表示第一信号电压和第二信号电压之差的绝对值电压。 半导体计算电路包括：第一MOS晶体管，具有浮动栅极和与浮动栅极电容耦合的控制栅极; 具有浮置栅极和与栅极电容耦合的控制栅极的第二MOS晶体管，其源极连接到第一MOS晶体管的源极; 写入电路，其中施加到第一和第二MOS晶体管的控制栅极的规定电压将第一MOS晶体管的浮置栅极处的电位设置为等于第一信号电压的值，并且还将电位设置在 第二MOS晶体管的浮置栅极等于通过从规定电压减去第一信号电压而获得的值; 以及差分电压计算电路，用于计算表示通过从规定电压减去第二信号电压而获得的值的电压，并且其中：在通过写入电路设置第一和第二MOS晶体管之后，当差分电压计算的输出电压 电路施加到第一MOS晶体管的控制栅极，同时将第二信号电压施加到第二MOS晶体管的控制栅极，绝对值电压表示第一信号电压和第二信号电压之间的差 被输出。

公开(公告)号：US06334120B1

公开(公告)日：2001-12-25

申请号：US09041531

申请日：1998-03-13

申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Tatsuo Morimoto

发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Tatsuo Morimoto

IPC分类号： G06F1518

CPC分类号： G06N3/063

摘要： A semiconductor device capable of executing size comparison operations on a plurality of data at high speed and in real time and using simple circuitry. An inverter circuit group is used containing a plurality of inverter circuits constructed using neuron MOS transistors. Predetermined signal voltages are applied from the exterior to the first input gates of the inverter circuits, and the output signals of all inverters contained in the inverter circuit group are inputted into a first logical arithmetic circuit and a second logical arithmetic circuit, and the output signal of the first logical arithmetic circuit is inputted into a third logical arithmetic circuit controlled by the output signal of the second logical arithmetic circuit, and the output of the third logical arithmetic circuit is fed back to the second input gates of the inverter circuits contained in the inverter circuit group. Bye use of the output signals of the inverter circuit groups, the position having the maximum voltage among the signal voltages inputted into the inverter circuit groups is specified.

摘要翻译： 一种半导体器件，其能够以高速和实时的方式对多个数据执行大小比较操作，并且使用简单的电路。 使用包含使用神经元MOS晶体管构造的多个反相器电路的逆变器电路组。 从外部向逆变器电路的第一输入门施加预定信号电压，并且包含在逆变器电路组中的所有反相器的输出信号被输入到第一逻辑运算电路和第二逻辑运算电路中，并且输出信号 第一逻辑运算电路的输出被输入到由第二逻辑运算电路的输出信号控制的第三逻辑运算电路中，并且第三逻辑运算电路的输出反馈到包含在第二逻辑运算电路中的反相器电路的第二输入门 逆变电路组。 指定逆变器电路组的输出信号，输入到逆变器电路组的信号电压中具有最大电压的位置。

公开(公告)号：US06456992B1

公开(公告)日：2002-09-24

申请号：US08913680

申请日：1997-11-07

申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Tatsuo Morimoto ,  Ryu Kaiwara

发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Tatsuo Morimoto ,  Ryu Kaiwara

IPC分类号： G06N304

CPC分类号： G06N3/0635

摘要： A semiconductor arithmetic circuit which compares the magnitudes of a plurality of data with each other in real time by using a simple circuit. The semiconductor arithmetic circuit containing one or more neuron MOS transistors each having a plurality of input gate electrodes has an inverter circuit group of a plurality of inverter circuit each of which is constituted of neuron MOS transistors and a means for applying a prescribed signal voltage to at least one first input gate of the inverter circuit. The out put signals of all the inverters in the inverter circuit group, the output signal of a logical operation circuit generated by passing the output signals of the inverters through a multistage inverter circuit and inputting them into the logical operation circuit, or the output signal of a multistage inverter circuit generated by passing the output signal of the logical operation circuit through the multistage inverter circuit is fed back to at least one second input gate of the inverter circuit in the inverter circuit group.

摘要翻译： 一种半导体运算电路，其通过使用简单电路实时地比较多个数据的大小。包含一个或多个具有多个输入栅电极的神经元MOS晶体管的半导体运算电路具有逆变器电路组 多个反相器电路，每个反相器电路由神经元MOS晶体管构成，以及用于将规定的信号电压施加到逆变器电路的至少一个第一输入栅极的装置。 逆变器电路组中的所有反相器的输出信号，通过使多级逆变器电路通过反相器的输出信号并将其输入逻辑运算电路而产生的逻辑运算电路的输出信号，或者输出信号 通过将逻辑运算电路的输出信号通过多级逆变器电路而产生的多级逆变器电路被反馈到逆变器电路组中的逆变器电路的至少一个第二输入门。

公开(公告)号：US06459312B2

公开(公告)日：2002-10-01

申请号：US09919926

申请日：2001-08-02

申请人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

发明人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

IPC分类号： H03L700

CPC分类号： H03K3/0315 ,  H03K3/354 ,  H03K5/133 ,  H03K2005/00045 ,  H03L7/0812 ,  H03L7/0995 ,  H03L2207/06

摘要： The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.

摘要翻译： 通过其中信号输入端子通过第一电容器连接到读出放大器的输入端的电路来解决抖动量增加与延迟量增加的问题，控制输入端子通过第二电容器连接到输入端 读出放大器的端子和读出放大器的输入端与第一和第二电容器之间的公共连接点是浮动节点，并且其中通过信号输入端施加到读出放大器的输入端的信号是垂直的 至少在感测放大器的判定阈值附近，施加到控制输入端子的控制信号移位，从而控制输出的延迟量。

公开(公告)号：US6127852A

公开(公告)日：2000-10-03

申请号：US110014

申请日：1998-07-02

申请人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

发明人： Katsuhisa Ogawa ,  Tadahiro Ohmi ,  Tadashi Shibata

IPC分类号： G01D1/12 ,  G06G7/12 ,  G06G7/122 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H03D1/00

CPC分类号： G06G7/122

摘要： To retrieve analog signals at high precision by a maximum or minimum position detection parallel signal processing circuit, a plurality of circuit units in each of which a gate of a transistor is connected to a signal input terminal through first capacitive means, a common connecting point of the gate and the first capacitive means is connected to one terminal side of second capacitive means, and control means, for fluctuating a voltage on the other terminal side of the second capacitive means so as to further increase or decrease a drain current in correspondence to an increase or decrease in the drain current is connected between the drain and the other terminal side of the second capacitive means are provided, a source of each transistor of the plurality of circuit units is commonly connected and is connected to a constant current source, and the maximum or minimum voltage position detection with respect to a signal voltage which is applied to each signal input terminal is performed by a voltage on the other terminal side of the second capacitive means.

摘要翻译： 为了通过最大或最小位置检测并行信号处理电路以高精度检索模拟信号，通过第一电容装置将晶体管的栅极连接到信号输入端的多个电路单元中的多个电路单元， 栅极和第一电容装置连接到第二电容装置的一个端子侧，以及控制装置，用于使第二电容装置的另一个端子侧的电压波动，以进一步增加或减少对应于 在第二电容装置的漏极和另一个端子侧之间连接漏极电流的增加或减少，多个电路单元中的每个晶体管的源极共同连接并连接到恒定电流源，并且 执行相对于施加到每个信号输入端子的信号电压的最大或最小电压位置检测 通过第二电容装置的另一个端子侧的电压。

公开(公告)号：US5939925A

公开(公告)日：1999-08-17

申请号：US930508

申请日：1997-11-07

申请人： Tadashi Shibata ,  Tadahiro Ohmi ,  Ning Mei Yu ,  Tsutomu Nakai

发明人： Tadashi Shibata ,  Tadahiro Ohmi ,  Ning Mei Yu ,  Tsutomu Nakai

IPC分类号： G06F17/16 ,  G06J1/00 ,  G06K9/64 ,  G06G7/12

CPC分类号： G06K9/64 ,  G06F17/16 ,  G06J1/00

摘要： A semiconductor operational circuit conducts real-time analog vector operations to permit the determination of the center of gravity of an image of a moving object. The circuit employs a first processing stage utilizing CMOS source follower circuits to perform weighted linear sum operations on the analog signals. A second processing stage utilizes comparator circuitry to perform comparison operations involving data from the weighted-sum and non-weighted-sum operations. A third processing stage utilizes exclusive OR gates to provide digital data outputs based on the comparison operation results.

摘要翻译： PCT No.PCT / JP96 / 00883 Sec。 371日期：1997年11月7日 102（e）日期1997年11月7日PCT 1996年4月1日PCT PCT。 出版物WO96 / 30827 日期1996年10月3日半导体运算电路进行实时模拟矢量运算，以确定移动物体的图像的重心。 电路采用利用CMOS源极跟随器电路的第一处理级，对模拟信号执行加权线性和运算。 第二处理阶段利用比较器电路执行涉及来自加权和和非加权和运算的数据的比较运算。 第三处理级利用异或门来提供基于比较运算结果的数字数据输出。

公开(公告)号：US5683072A

公开(公告)日：1997-11-04

申请号：US508405

申请日：1995-07-31

申请人： Tadahiro Ohmi ,  Tadashi Shibata ,  Masaru Umeda

发明人： Tadahiro Ohmi ,  Tadashi Shibata ,  Masaru Umeda

IPC分类号： C23C8/14 ,  C23C14/34 ,  C23C14/35 ,  C23C14/56 ,  C23C16/44 ,  F16K31/02 ,  F16K51/02 ,  H01J37/32 ,  F16K3/18

CPC分类号： H01J37/32174 ,  C23C14/34 ,  C23C14/35 ,  C23C14/56 ,  C23C14/564 ,  C23C16/4404 ,  C23C8/14 ,  F16K31/02 ,  F16K51/02 ,  H01J37/32082 ,  H01J2237/186

摘要： A gate valve for a thin film forming apparatus. The gate valve includes two adjoining low-pressure chambers and a wall separating the two chambers. The wall includes an aperture and a thin plate for covering the aperture. The thin plate is movable in a direction substantially parallel to the plate surface. The gate valve further includes a voltage supply for applying a direct current between the thin plate and the wall.

摘要翻译： 一种用于薄膜形成装置的闸阀。 闸阀包括两个相邻的低压室和分隔两个室的壁。 该壁包括孔和用于覆盖孔的薄板。 薄板可以在基本上平行于板表面的方向上移动。 闸阀还包括用于在薄板和壁之间施加直流电的电压源。