公开(公告)号：US07314805B2

公开(公告)日：2008-01-01

申请号：US11519907

申请日：2006-09-13

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21/331

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

摘要翻译： 用于形成源区和漏区（S和D）的掺杂剂离子的注入步骤被划分为用于与阱区（3）形成ap / n结的掺杂剂离子的一次注入，并且一次注入掺杂剂离子 不影响源极和漏极区域（S和D）之间的p / n结的位置以及具有浅的注入深度和大的注入量的阱区域。 在对掺杂剂进行激活热处理之后，将源极/漏极区域的表面制成硅化钴12，使得源极/漏极区域（S和D）可以具有低电阻，并且ap / n结泄漏可以 减少

公开(公告)号：US07132341B2

公开(公告)日：2006-11-07

申请号：US09974814

申请日：2001-10-12

申请人： Masashi Sahara ,  Fumiaki Endo ,  Masanori Kojima ,  Katsuhiro Uchimura ,  Hideaki Kanazawa ,  Masakazu Sugiura

发明人： Masashi Sahara ,  Fumiaki Endo ,  Masanori Kojima ,  Katsuhiro Uchimura ,  Hideaki Kanazawa ,  Masakazu Sugiura

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L29/665 ,  G11C11/412 ,  H01L21/2633 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/32132 ,  H01L27/11 ,  H01L27/1104

摘要： In a high-performance semiconductor integrated circuit, the standby current is reduced by preventing current leakage in a semiconductor integrated circuit device, for example, the memory cell of an SRAM. A gate electrode G is formed on semiconductor substrate 1 and n+-type semiconductor regions 17 (source/drain regions) are formed in the semiconductor substrate on both sides of this gate electrode. Within the same apparatus and under near-vacuum conditions, a depth of 2.5 nm or less is etched away from the surfaces of the source/drain regions and gate electrode, a film of Co is then formed on the source/drain regions, and thermal processing is applied to form CoSi2 layer 19a. As a result, current leakage in the memory cell can be prevented and this method can be applied to semiconductor integrated circuit devices that have low current consumption or are battery-driven.

摘要翻译： 在高性能半导体集成电路中，通过防止半导体集成电路器件例如SRAM的存储单元中的电流泄漏来降低待机电流。 栅电极G形成在半导体衬底1上，并且在该栅电极两侧的半导体衬底中形成n + +型半导体区17（源/漏区）。 在相同的装置内和在近真空条件下，从源极/漏极区域和栅极电极的表面蚀刻2.5nm或更小的深度，然后在源极/漏极区域上形成Co膜，并且热源 施加处理以形成CoSi 2层19a。 结果，可以防止存储单元中的电流泄漏，并且该方法可以应用于具有低电流消耗或电池驱动的半导体集成电路器件。

公开(公告)号：US07064040B2

公开(公告)日：2006-06-20

申请号：US11169574

申请日：2005-06-30

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and’ a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

公开(公告)号：US20050250269A1

公开(公告)日：2005-11-10

申请号：US11169574

申请日：2005-06-30

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/338 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

公开(公告)号：US20050239258A1

公开(公告)日：2005-10-27

申请号：US11169585

申请日：2005-06-30

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

摘要翻译： 用于形成源区和漏区（S和D）的掺杂剂离子的注入步骤被划分为用于与阱区（3）形成ap / n结的掺杂剂离子的一次注入，并且一次注入掺杂剂离子 不影响源极和漏极区域（S和D）之间的p / n结的位置以及具有浅的注入深度和大的注入量的阱区域。 在对掺杂剂进行激活热处理之后，将源极/漏极区域的表面制成硅化钴12，使得源极/漏极区域（S和D）可以具有低电阻，并且ap / n结泄漏可以 减少

公开(公告)号：US06610564B2

公开(公告)日：2003-08-26

申请号：US09910794

申请日：2001-07-24

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L218238

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

公开(公告)号：US5764956A

公开(公告)日：1998-06-09

申请号：US554780

申请日：1995-11-07

申请人： Yutaka Akahori ,  Hideaki Ogata ,  Yasushi Nakaoka ,  Masanori Kojima

发明人： Yutaka Akahori ,  Hideaki Ogata ,  Yasushi Nakaoka ,  Masanori Kojima

IPC分类号： G06F9/455

CPC分类号： G06F9/45504

摘要： An emulator that emulates the operation of a target machine on an execution machine is disclosed. The execution module prepared for each function of the target machine is called via a dispatcher from a kernel. A calling address is registered in a dispatcher table by the execution module when each execution module is loaded. Inputs from a keyboard causes a hardware interrupt resulting in the calling of a keyboard emulator. After a converted key code is stored in a buffer, an interrupt controller emulator is called by intermodule communication. The interrupt controller emulator requests a virtual interrupt for the kernel. The keyboard emulator is called again and the key code stored in the buffer is transmitted to the application program.

摘要翻译： 公开了一种在执行机器上模拟目标机器的操作的仿真器。 通过内核的调度程序调用为目标机器的每个功能准备的执行模块。 当每个执行模块被加载时，执行模块在调度表中注册一个调用地址。 来自键盘的输入引起硬件中断，导致键盘仿真器的调用。 转换的密钥代码存储在缓冲区中后，通过模块间通信调用中断控制器仿真器。 中断控制器仿真器为内核请求虚拟中断。 再次调用键盘仿真器，将存储在缓冲器中的键码传输到应用程序。

公开(公告)号：US07074665B2

公开(公告)日：2006-07-11

申请号：US10701423

申请日：2003-11-06

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

公开(公告)号：US5815221A

公开(公告)日：1998-09-29

申请号：US565249

申请日：1995-11-30

申请人： Masanori Kojima ,  Ko Nishino ,  Yasuhito Myoi ,  Masaaki Tanaka ,  Teruo Miyamoto ,  Fumio Suzuki ,  Fumio Itoh ,  Yoshisuke Otsuru

发明人： Masanori Kojima ,  Ko Nishino ,  Yasuhito Myoi ,  Masaaki Tanaka ,  Teruo Miyamoto ,  Fumio Suzuki ,  Fumio Itoh ,  Yoshisuke Otsuru

IPC分类号： G02F1/13 ,  G02B27/28 ,  G02F1/1335 ,  G02F1/13357 ,  G02F1/1347 ,  H04N9/31

CPC分类号： H04N9/3188 ,  H04N9/3105 ,  G02F1/133536 ,  G02F1/13362 ,  G02F2001/13355

摘要： A polarizing beam splitter extracts orthogonally polarized light beams from natural light and distributes those to liquid crystal panels, which modulate polarization states of those polarized light beams in accordance with a luminance signal and chrominance signals of video signals, respectively. The modulated light beams are combined by the same polarizing beam splitter, and the combined light is enlarged and projected onto a screen by a projection lens, to reproduce a projected image.

摘要翻译： 偏振光束分离器从自然光中提取正交偏振光束，并将其分配到液晶面板，液晶面板分别根据视频信号的亮度信号和色度信号调制偏振光束的偏振状态。 调制光束由相同的偏振分束器组合，并且组合的光被投影透镜放大并投影到屏幕上，以再现投影图像。

公开(公告)号：US5426469A

公开(公告)日：1995-06-20

申请号：US181543

申请日：1994-01-14

申请人： Masanori Kojima

发明人： Masanori Kojima

IPC分类号： H04N5/21 ,  H04N9/78 ,  H04N9/77

CPC分类号： H04N9/78

摘要： A video signal processor is used in connection with a television set or similar apparatus for processing a video signal input for every horizontal line period. A video signal is processed by operations such as comparison and addition of a video signal, a first delay signal which is delayed by a one-horizontal line period and a second delay signal which is delayed by a two-horizontal line period. Since there is a horizontal correlation in a video signal, it is possible to separate a color signal from a luminance signal and remove the noise component from the luminance signal by a predetermined operation. The comparison is substantially the subtraction of the signals which are output one after another by a delay of one horizontal line period in series, thereby avoiding such trouble as color edging.