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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20130049864A1

    公开(公告)日：2013-02-28

    申请号：US13589369

    申请日：2012-08-20

    申请人： Natsuki IKEHATA ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

    发明人： Natsuki IKEHATA ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

    IPC分类号： H03F3/45

    CPC分类号： G11C11/4091 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

    摘要翻译： 差分放大电路的输出信号特性得到改善。 当输入数据信号为低电平时，流过第一晶体管的电流将减小，并且第一电阻器和第二电阻器之间的连接（节点）的电位将增加。 该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。 当输入数据信号为高电平时，第一晶体管的电流增加，因此节点处的电位降低。 因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。 因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。

    Semiconductor integrated circuit
    2.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US08723291B2

    公开(公告)日：2014-05-13

    申请号：US13592949

    申请日：2012-08-23

    申请人： Toshiaki Yonezu ,  Takeshi Iwamoto ,  Shigeki Obayashi ,  Masashi Arakawa ,  Kazushi Kono

    发明人： Toshiaki Yonezu ,  Takeshi Iwamoto ,  Shigeki Obayashi ,  Masashi Arakawa ,  Kazushi Kono

    IPC分类号： H01L23/62

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first the via hole wiring is surrounded.

    摘要翻译： 一种半导体集成电路，其可以使用电熔丝执行可靠的浮雕处理。 半导体集成电路包括熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。 保险丝布线被超过预定值的电流切断。 第一电极焊盘连接到熔丝布线的一侧，第二电极焊盘连接到熔丝布线的另一侧，污染控制层通过绝缘体形成在熔丝布线的上层和下层中 层。 在熔丝配线中，在第一通孔配线的外侧形成有一对的第二通孔配线，以使第一通孔配线被包围。

    Semiconductor integrated circuit device
    8.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08803610B2

    公开(公告)日：2014-08-12

    申请号：US13589369

    申请日：2012-08-20

    申请人： Natsuki Ikehata ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

    发明人： Natsuki Ikehata ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

    IPC分类号： H03F3/45

    CPC分类号： G11C11/4091 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

    摘要翻译： 差分放大电路的输出信号特性得到改善。 当输入数据信号为“低”时，流过第一晶体管的电流将减小，并且第一电阻和第二电阻之间的连接（节点）的电位将增加。 该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。 当输入数据信号为“高”时，第一晶体管的电流增加，因此节点处的电位减小。 因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。 因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    9.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20130049166A1

    公开(公告)日：2013-02-28

    申请号：US13592949

    申请日：2012-08-23

    申请人： Toshiaki YONEZU ,  Takeshi Iwamoto ,  Shigeki Obayashi ,  Masashi Arakawa ,  Kazushi Kono

    发明人： Toshiaki YONEZU ,  Takeshi Iwamoto ,  Shigeki Obayashi ,  Masashi Arakawa ,  Kazushi Kono

    IPC分类号： H01L23/62

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by a current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, a second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first via hole wiring is surrounded.

    摘要翻译： 一种半导体集成电路，其可以使用电熔丝执行可靠的浮雕处理。 半导体集成电路包括熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。 保险丝布线被超过预定值的电流切断。 第一电极焊盘连接到熔丝布线的一侧，第二电极焊盘连接到熔丝布线的另一侧，污染控制层通过绝缘体形成在熔丝布线的上层和下层中 层。 在保险丝布线中，在第一通孔布线的外侧形成有一对第二通孔布线，使得第一通孔布线被包围。