公开(公告)号：US06751116B2

公开(公告)日：2004-06-15

申请号：US10233486

申请日：2002-09-04

申请人： Naoki Kuroda ,  Masashi Agata

发明人： Naoki Kuroda ,  Masashi Agata

IPC分类号： G11C1124

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/2281

摘要： A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

摘要翻译： 包括要访问的存储单元的第一晶体管，第一位线对，第一列选择开关和数据线对的路径的端口A与包括存储器单元的第二晶体管的路径的端口B交错 要被访问的第二位线对，第二列选择开关和数据线对在时钟的两个周期中。 读取放大器将从位线对传送的数据放大到数据线对，并在时钟的一个周期内将结果数据输出到输入/输出缓冲器。 输入/输出缓冲器在时钟的一个周期内将从读取放大器接收到的数据输出到外部。

公开(公告)号：US07031199B2

公开(公告)日：2006-04-18

申请号：US10815709

申请日：2004-04-02

申请人： Naoki Kuroda ,  Masashi Agata

发明人： Naoki Kuroda ,  Masashi Agata

IPC分类号： G11C11/34

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/2281

摘要： A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

公开(公告)号：US06788565B2

公开(公告)日：2004-09-07

申请号：US10394262

申请日：2003-03-24

申请人： Masashi Agata ,  Kazunari Takahashi ,  Masanori Shirahama ,  Naoki Kuroda ,  Hiroyuki Sadakata ,  Ryuji Nishihara

发明人： Masashi Agata ,  Kazunari Takahashi ,  Masanori Shirahama ,  Naoki Kuroda ,  Hiroyuki Sadakata ,  Ryuji Nishihara

IPC分类号： G11C1140

CPC分类号： G11C11/405 ,  H01L27/108

摘要： A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.

摘要翻译： 半导体存储器件具有多个存储单元，每个存储单元具有第一晶体管，第二晶体管具有连接到第一晶体管的源极或漏极的一部分的源极或漏极;以及第三晶体管，源极或漏极连接到第一晶体管， 第一晶体管的源极或漏极的另一部分。 第一晶体管在其通道中累积从第二和第三晶体管传送的电荷。

公开(公告)号：US6137713A

公开(公告)日：2000-10-24

申请号：US420576

申请日：1999-10-19

申请人： Naoki Kuroda ,  Masashi Agata ,  Kazunari Takahashi

发明人： Naoki Kuroda ,  Masashi Agata ,  Kazunari Takahashi

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C11/24 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/108 ,  G11C11/24 ,  G11C11/405 ,  G11C5/02 ,  G11C5/063 ,  H01L27/10885

摘要： Over an active region with two bent portions on a semiconductor substrate, first and second word lines extend to cross these bent portions and to be vertically spaced apart from each other. Around at the center of the active region, a capacitor for storing data thereon and a capacitor contact are formed. A first bit line contact, which is connected to the active region, is formed on the opposite side to the capacitor contact across the first word line over the active region. A second bit line contact, which is also connected to the active region, is formed on the opposite side to the capacitor contact across the second word line over the active region. These first and second bit line contacts are provided substantially symmetrically about the center of the memory cell. In a pair of memory cells adjacent to each other along bit lines, one vertical end of the active region in one of the memory cells is continuous with an associated vertical end of the active region in the other memory cell. And each of the first and second bit line contacts is shared between an adjacent pair of memory cells.

摘要翻译： 在半导体衬底上具有两个弯曲部分的有源区域上，第一和第二字线延伸以跨越这些弯曲部分并且彼此垂直间隔开。 在有源区域的中心附近形成用于存储数据的电容器和电容器触点。 连接到有源区域的第一位线触点形成在跨过有源区域的跨第一字线的电容器触点的相反侧。 还连接到有源区的第二位线触点形成在跨过有源区的跨越第二字线的电容器触点的相反侧。 这些第一和第二位线触点基本上围绕存储器单元的中心对称地设置。 在沿着位线彼此相邻的一对存储单元中，一个存储单元中的有源区的一个垂直端与另一个存储单元中的有源区的相关联的垂直端连续。 并且第一和第二位线触点中的每一个在相邻的一对存储单元之间共享。

公开(公告)号：US06327210B1

公开(公告)日：2001-12-04

申请号：US09711884

申请日：2000-11-15

申请人： Naoki Kuroda ,  Masashi Agata

发明人： Naoki Kuroda ,  Masashi Agata

IPC分类号： G11C800

CPC分类号： G11C11/406

摘要： A semiconductor memory device allowing for high-speed random accesses and yet requiring no external refreshing by performing internal refreshing automatically and efficiently. If no external commands /RE or /WT, instructing that data should be read out or written on a memory cell, are given, the output signal of a first AND gate is asserted. A second AND gate is provided to obtain a logical product of the output signal of the first AND gate and an internal refresh signal INTREF representing that refreshing may be performed internally and independently. The output signal REFEN of the second AND gate is used as a reference signal for automatic refreshing. Thus, refreshing is performed automatically by taking advantage of a window during which no external commands are input. And when an external command is input, refreshing is canceled.

摘要翻译： 半导体存储器件允许高速随机存取，并且通过自动而有效地执行内部刷新而不需要外部刷新。 如果没有指定数据应该被读出或写入存储单元的外部命令/ RE或/ WT，则第一个与门的输出信号被断言。 提供第二与门以获得第一与门的输出信号和内部刷新信号INTREF的逻辑积，表示刷新可以在内部和独立地执行。 第二与门的输出信号REFEN用作自动刷新的参考信号。 因此，通过利用没有输入外部命令的窗口来自动执行刷新。 当输入外部命令时，刷新被取消。

公开(公告)号：US06243301B1

公开(公告)日：2001-06-05

申请号：US09447674

申请日：1999-11-23

申请人： Masashi Agata ,  Naoki Kuroda ,  Makoto Kojima

发明人： Masashi Agata ,  Naoki Kuroda ,  Makoto Kojima

IPC分类号： G11C700

CPC分类号： G11C29/848

摘要： Redundancy function with excellent repair efficiency is implemented by specifying a single address for a semiconductor memory device of a multi-bit accessing type. A memory array includes a plurality of memory segments associated with respective addresses. Each memory segment is coupled to a data bus multiplexer via an associated first data bus. A sub-data bus, which includes a larger number of signal lines than that of those included in the first data bus, is provided for each memory segment. These signal lines are connected to associated bit lines in each memory sub-array. A data bus switching circuit is associated with each memory segment to electrically connect the respective signal lines included in the first data bus to the counterparts included in the sub-data bus to meet a predetermined relationship by cutting one of fuses off. In this manner, redundancy function with excellent repair efficiency is implementable on a bit-by-bit basis, not on an address basis.

摘要翻译： 通过为多位访问类型的半导体存储器件指定单个地址来实现具有优异修复效率的冗余功能。 存储器阵列包括与相应地址相关联的多个存储器段。 每个存储器段通过相关联的第一数据总线耦合到数据总线多路复用器。 为每个存储器段提供了包括比包括在第一数据总线中的信号线数量更多的信号线的子数据总线。 这些信号线连接到每个存储器子阵列中的相关位线。 数据总线切换电路与每个存储器段相关联，以将包括在第一数据总线中的各个信号线与包含在子数据总线中的对应电路电连接，以通过切断熔断器之一来满足预定的关系。 以这种方式，具有优异的修复效率的冗余功能可以逐位地实现，而不是基于地址。

公开(公告)号：US06226223B1

公开(公告)日：2001-05-01

申请号：US09511901

申请日：2000-02-23

申请人： Masanori Shirahama ,  Tsutomu Fujita ,  Masashi Agata ,  Kazunari Takahashi ,  Naoki Kuroda

发明人： Masanori Shirahama ,  Tsutomu Fujita ,  Masashi Agata ,  Kazunari Takahashi ,  Naoki Kuroda

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/24 ,  G11C11/4076

摘要： In a semiconductor memory device with multiple memory cells, each including a charge storage device and two transfer devices for transferring its charge, these memory cells are accessible with no select signal provided externally. The memory device includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of first word lines and one of second word lines are activated alternately. Specifically, the first clock signal makes a memory cell accessible through a first bit line by activating the first word line and first transistor, while the second clock signal makes the memory cell accessible through a second bit line by activating the second word line and second transistor.

摘要翻译： 在具有多个存储器单元的半导体存储器件中，每个存储单元包括一个电荷存储器件和两个用于传送其电荷的转移器件，这些存储器单元是可以被访问的，没有从外部提供的选择信号。 存储器件包括用于产生第一和第二互补时钟信号的时钟发生器。 响应于第一和第二时钟信号，交替地激活第一字线和第二字线之一中的一个。 具体地，第一时钟信号通过激活第一字线和第一晶体管使得可通过第一位线访问存储单元，而第二时钟信号通过激活第二字线和第二晶体管使存储单元通过第二位线访问 。

公开(公告)号：US06181620B2

公开(公告)日：2001-01-30

申请号：US09484023

申请日：2000-01-18

申请人： Masashi Agata ,  Kazunari Takahashi ,  Tsutomu Fujita ,  Naoki Kuroda ,  Toshio Yamada

发明人： Masashi Agata ,  Kazunari Takahashi ,  Tsutomu Fujita ,  Naoki Kuroda ,  Toshio Yamada

IPC分类号： G11C1124

CPC分类号： G11C11/405 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094

摘要： The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.

摘要翻译： 本发明的半导体存储装置包括具有两个晶体管和一个存储电容器的存储单元。 每个存储单元与第一字线和用于第一端口的第一位线和用于第二端口的第二字线和第二位线连接。 第一位线和第二位线以开放位线配置交替布置。 在半导体存储装置的动作中，在对第一读出放大器的第一预定电荷进行预充电的第一预充电信号或激活第一读出放大器的第一读出放大器的激活信号保持为有效状态的期间内， 第二位线和用于激活第二读出放大器的第二读出放大器激活信号都处于非活动状态。

公开(公告)号：US06169684A

公开(公告)日：2001-01-02

申请号：US09495473

申请日：2000-02-01

申请人： Kazunari Takahashi ,  Masashi Agata ,  Naoki Kuroda ,  Tsutomu Fujita

发明人： Kazunari Takahashi ,  Masashi Agata ,  Naoki Kuroda ,  Tsutomu Fujita

IPC分类号： G11C1500

CPC分类号： G11C11/4097 ,  G06F12/0893 ,  G06F2212/3042 ,  G11C11/005

摘要： A cache memory including a first memory array and a main memory including a second memory array are integrated together on the same semiconductor substrate. Each memory cell in the first memory array is of a 2Tr1C type including: first and second transistors, the sources of which are connected together; and a data storage capacitor, one of the two electrodes of which is connected to the common source of the first and second transistors. Each memory cell in the second memory array is of a 1Tr1C type including: a third transistor; and a data storage capacitor, one of the two electrodes of which is connected to the source of the third transistor.

摘要翻译： 包括第一存储器阵列和包括第二存储器阵列的主存储器的高速缓存存储器集成在同一半导体衬底上。 第一存储器阵列中的每个存储单元是2Tr1C类型，包括：第一和第二晶体管，其源极连接在一起; 以及数据存储电容器，其两个电极中的一个连接到第一和第二晶体管的公共源。 第二存储器阵列中的每个存储单元是1Tr1C类型，包括：第三晶体管; 以及数据存储电容器，其两个电极中的一个连接到第三晶体管的源极。

公开(公告)号：US07561080B2

公开(公告)日：2009-07-14

申请号：US11790737

申请日：2007-04-27

申请人： Naoki Yamada ,  Naoki Kuroda

发明人： Naoki Yamada ,  Naoki Kuroda

IPC分类号： H03M9/00

CPC分类号： H03M1/1071

摘要： The semiconductor integrated circuit includes: a plurality of macro cells; and a serial-parallel conversion circuit for converting a serial signal inputted from outside to generate parallel selection control signals during testing, or an A/D conversion circuit for converting an analog signal inputted from outside to generate digital selection control signals during testing. One or more among, the plurality of macro cells are selected based on the selection control signals and brought to a test operation state.

摘要翻译： 半导体集成电路包括：多个宏小区; 以及用于转换从外部输入的串行信号以在测试期间产生并行选择控制信号的串并转换电路，或用于转换从外部输入的模拟信号以在测试期间产生数字选择控制信号的A / D转换电路。 基于选择控制信号选择多个宏小区中的一个或多个，并进入测试操作状态。