公开(公告)号：US06567337B1

公开(公告)日：2003-05-20

申请号：US09607897

申请日：2000-06-30

Applicant: Milo D. Sprague ,  David K. Li ,  Robert J. Murray

Inventor： Milo D. Sprague ,  David K. Li ,  Robert J. Murray

IPC: G11C800

CPC classification number: G11C7/1093 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A pulsed circuit topology to perform a memory array write operation. A write enable pulse width control circuit is responsive to a pulsed clock signal to generate a pulsed write enable signal and a write data path circuit is provided to output a write data signal. The write enable pulse width control circuit and the write data path circuit together control a write operation to a memory cell.

Abstract translation: 用于执行存储器阵列写入操作的脉冲电路拓扑。 写使能脉冲宽度控制电路响应于脉冲时钟信号以产生脉冲写使能信号，并且提供写数据通路电路以输出写数据信号。 写入使能脉冲宽度控制电路和写入数据路径电路一起控制对存储器单元的写入操作。

公开(公告)号：US06531897B1

公开(公告)日：2003-03-11

申请号：US09608389

申请日：2000-06-30

Applicant: Mark S. Milshtein ,  Milo D. Sprague ,  Terry I. Chappell ,  Thomas D. Fletcher

Inventor： Mark S. Milshtein ,  Milo D. Sprague ,  Terry I. Chappell ,  Thomas D. Fletcher

IPC: H03K19096

CPC classification number: H03K19/0966

Abstract: A global clock self-timed circuit initiates a precharge pulse in response to which a domino node is precharged. A self-terminating precharge circuit coupled to the global clock self-timed circuit and the domino node terminates the precharge pulse after the domino node has been precharged.

Abstract translation: 全局时钟自定时电路启动预充电脉冲，响应于预充电脉冲。 耦合到全局时钟自定时电路和多米诺骨架的自终端预充电电路在多米诺骨牌节点预充电之后终止预充电脉冲。

公开(公告)号：US06496038B1

公开(公告)日：2002-12-17

申请号：US09608857

申请日：2000-06-30

Applicant: Milo D. Sprague ,  Rajesh Kumar ,  Robert J. Murray

Inventor： Milo D. Sprague ,  Rajesh Kumar ,  Robert J. Murray

IPC: H03K19096

CPC classification number: H03K19/0963 ,  H03K5/1534

Abstract: A pulsed circuit topology including a pulsed domino flip-flop. A circuit includes a domino logic gate having a domino output node responsive to input data during an evaluate pulse. Reset circuitry initiates and self-terminates a reset pulse during which the domino output node is precharged. A latch responsive to a first pulsed clock input signal is provided to latch data indicated at the domino output node.

Abstract translation: 包括脉冲多米诺触发器的脉冲电路拓扑。 电路包括具有在评估脉冲期间响应于输入数据的多米诺骨牌输出节点的多米诺骨牌逻辑门。 复位电路启动并自动终止多米诺骨牌输出节点预充电的复位脉冲。 提供响应于第一脉冲时钟输入信号的锁存器来锁存在多米诺骨牌输出节点处指示的数据。

公开(公告)号：US06239621B1

公开(公告)日：2001-05-29

申请号：US09473974

申请日：1999-12-29

Applicant: Mark S. Milshtein ,  Milo D. Sprague

Inventor： Mark S. Milshtein ,  Milo D. Sprague

IPC: H03K19096

CPC classification number: H03K19/0963

Abstract: A method is provided for precharging a node in an integrated circuit in which the node is precharged a first predetermined delay after the node evaluates and, thereafter, the precharge ceases after a second shorter predetermined delay.

Abstract translation: 提供了一种用于对集成电路中的节点进行预充电的方法，其中节点在节点评估之后被预充电第一预定延迟，之后在第二较短的预定延迟之后停止预充电。

公开(公告)号：US06204714B1

公开(公告)日：2001-03-20

申请号：US09159548

申请日：1998-09-24

Applicant: Mark S. Milshtein ,  Thomas D. Fletcher ,  Kevin (Xia) Dai ,  Terry I. Chappell ,  Milo D. Sprague

Inventor： Mark S. Milshtein ,  Thomas D. Fletcher ,  Kevin (Xia) Dai ,  Terry I. Chappell ,  Milo D. Sprague

IPC: H03K104

CPC classification number: H03K5/133 ,  H03K5/00006 ,  H03K5/156 ,  H03K2005/00058

Abstract: A variable width pulse generator. The pulse generator includes a pulse circuit responsive to a reset signal to provide a pulse circuit signal. A variable delay reset loop path, coupled to the pulse circuit, is responsive to the pulse circuit signal to provide the reset signal. A control signal may vary the width of a pulse generated by the circuit by varying the length of a delay associated with the reset loop path. Both a coarse control signal, such as a signal that selectively removes a logic element in the reset loop path, and a fine control signal, such as a signal that controls a tunable delay element in the reset loop path, may be used to adjust the pulse width.

Abstract translation: 可变宽度脉冲发生器。 脉冲发生器包括响应于复位信号的脉冲电路以提供脉冲电路信号。 耦合到脉冲电路的可变延迟复位环路径响应脉冲电路信号以提供复位信号。 控制信号可以通过改变与复位环路径相关联的延迟的长度来改变由电路产生的脉冲的宽度。 可以使用诸如选择性地去除复位环路径中的逻辑元件的信号和诸如控制复位环路径中的可调谐延迟元件的信号的精细控制信号的粗略控制信号来调整 脉冲宽度。

公开(公告)号：US06542006B1

公开(公告)日：2003-04-01

申请号：US09608638

申请日：2000-06-30

Applicant: Milo D. Sprague ,  Robert J. Murray

Inventor： Milo D. Sprague ,  Robert J. Murray

IPC: H03K19096

CPC classification number: G06F9/3869 ,  H03K19/0966

Abstract: A reset first latching mechanism comprises a pulse chopper circuit responsive to a pulsed signal to control initiation and termination of a reset pulse wherein a domino node is to be precharged in response to the reset pulse. The reset first latching mechanism also includes domino logic circuit responsive to an evaluate pulse at an input to evaluate at the domino node based on a logic function performed by the domino logic circuit. The reset pulse is timed such that the reset pulse is completed before the evaluate at the domino node occurs.

Abstract translation: 复位第一锁存机构包括响应于脉冲信号的脉冲斩波电路，以控制复位脉冲的起始和终止，其中响应于复位脉冲将对多米诺骨架节点进行预充电。 复位第一闭锁机构还包括响应于输入处的评估脉冲的多米诺逻辑电路，以基于由多米诺逻辑电路执行的逻辑功能在多米诺骨牌节点处进行评估。 复位脉冲的定时使得复位脉冲在多米诺骨牌节点发生评估之前完成。