公开(公告)号：US07553748B2

公开(公告)日：2009-06-30

申请号：US11463812

申请日：2006-08-10

申请人： Sung-Ho Jang ,  Sang-Ho Song ,  Sung-Sam Lee ,  Min-Sung Kang ,  Won-Tae Park ,  Min-Young Shim

发明人： Sung-Ho Jang ,  Sang-Ho Song ,  Sung-Sam Lee ,  Min-Sung Kang ,  Won-Tae Park ,  Min-Young Shim

IPC分类号： H01L21/20

CPC分类号： H01L21/76897 ,  H01L27/10876 ,  H01L29/7834

摘要： According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

摘要翻译： 根据一个实施例，在衬底的沟道区上形成包括栅极绝缘图案，栅极图案和栅极掩模的栅极结构，以形成半导体器件。 在栅极结构的表面上形成间隔物。 在包括栅极结构的基板上形成绝缘层间图案，并且通过与基板的杂质区域对应的绝缘层间图案形成开口。 在开口中形成导电图案，其顶表面高于绝缘层间图案的顶表面。 因此，导电图案的上部从绝缘层间图案突出。 在绝缘层间图案上形成封盖图案，并且用封盖图案覆盖导电图案的突出部分的侧壁。 因此，封盖图案补偿了栅极掩模的厚度减小。

公开(公告)号：US20080179648A1

公开(公告)日：2008-07-31

申请号：US12000504

申请日：2007-12-13

申请人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

发明人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L29/94 ,  H01L21/823418 ,  H01L27/0629 ,  H01L27/105

摘要： A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first sidewall, a first drain region in the first region proximate to the second sidewall, an upper electrode on the second region and having a first sidewall and a second sidewall, a second source region in the second region proximate to the first sidewall of the upper electrode, and a second drain region in the second region proximate to the second sidewall of the upper electrode, wherein an impurity doping concentration of the first source region and the first drain region is greater than an impurity doping concentration of the second source region and the second drain region.

摘要翻译： 提供具有包括第一区域和第二区域的半导体衬底的半导体器件。 所述半导体器件还包括位于所述第一区域上并具有第一侧壁和第二侧壁的栅电极，所述第一区域中靠近所述第一侧壁的第一源极区域，所述第一区域中靠近所述第二侧壁的第一漏极区域， 在第二区域上的上电极，具有第一侧壁和第二侧壁，第二区域中靠近上电极的第一侧壁的第二区域，以及靠近第二侧壁的第二区域中的第二漏极区域 所述上电极，其中所述第一源极区域和所述第一漏极区域的杂质掺杂浓度大于所述第二源极区域和所述第二漏极区域的杂质掺杂浓度。

公开(公告)号：US20070042583A1

公开(公告)日：2007-02-22

申请号：US11463812

申请日：2006-08-10

申请人： Sung-Ho JANG ,  Sang-Ho SONG ,  Sung-Sam LEE ,  Min-Sung KANG ,  Won-Tae PARK ,  Min-Young SHIM

发明人： Sung-Ho JANG ,  Sang-Ho SONG ,  Sung-Sam LEE ,  Min-Sung KANG ,  Won-Tae PARK ,  Min-Young SHIM

IPC分类号： H01L21/3205

CPC分类号： H01L21/76897 ,  H01L27/10876 ,  H01L29/7834

摘要： According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

摘要翻译： 根据一个实施例，在衬底的沟道区上形成包括栅极绝缘图案，栅极图案和栅极掩模的栅极结构，以形成半导体器件。 在栅极结构的表面上形成间隔物。 在包括栅极结构的基板上形成绝缘层间图案，并且通过与基板的杂质区域对应的绝缘层间图案形成开口。 在开口中形成导电图案，其顶表面高于绝缘层间图案的顶表面。 因此，导电图案的上部从绝缘层间图案突出。 在绝缘层间图案上形成封盖图案，并且用封盖图案覆盖导电图案的突出部分的侧壁。 因此，封盖图案补偿了栅极掩模的厚度减小。

公开(公告)号：US08329539B2

公开(公告)日：2012-12-11

申请号：US11429890

申请日：2006-05-08

申请人： Dae-Won Ha ,  Kong-Soo Lee ,  Sung-Sam Lee ,  Sang-Hyun Lee ,  Min-Young Shim

发明人： Dae-Won Ha ,  Kong-Soo Lee ,  Sung-Sam Lee ,  Sang-Hyun Lee ,  Min-Young Shim

IPC分类号： H01L21/336 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66628 ,  H01L29/7834

摘要： In a semiconductor device having a recessed gate electrode and a method of fabricating the same, a channel trench is formed in a semiconductor substrate by etching the semiconductor substrate. A first semiconductor layer is formed on the semiconductor substrate that fills the channel trench. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer.

摘要翻译： 在具有凹陷栅电极的半导体器件及其制造方法中，通过蚀刻半导体衬底在半导体衬底中形成沟槽。 在半导体衬底上形成填充沟槽的第一半导体层。 第二半导体层形成在第一半导体层上，第二半导体层的杂质浓度低于第一半导体层。

公开(公告)号：US20070077713A1

公开(公告)日：2007-04-05

申请号：US11429890

申请日：2006-05-08

申请人： Dae-Won Ha ,  Kong-Soo Lee ,  Sung-Sam Lee ,  Sang-Hyun Lee ,  Min-Young Shim

发明人： Dae-Won Ha ,  Kong-Soo Lee ,  Sung-Sam Lee ,  Sang-Hyun Lee ,  Min-Young Shim

IPC分类号： H01L21/336

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66628 ,  H01L29/7834

摘要： In a semiconductor device having a recessed gate electrode and a method of fabricating the same, a channel trench is formed in a semiconductor substrate by etching the semiconductor substrate. A first semiconductor layer is formed on the semiconductor substrate that fills the channel trench. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer.

摘要翻译： 在具有凹陷栅电极的半导体器件及其制造方法中，通过蚀刻半导体衬底在半导体衬底中形成沟槽。 在半导体衬底上形成填充沟槽的第一半导体层。 第二半导体层形成在第一半导体层上，第二半导体层的杂质浓度低于第一半导体层。

公开(公告)号：US08004023B2

公开(公告)日：2011-08-23

申请号：US12000504

申请日：2007-12-13

申请人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

发明人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

IPC分类号： H01L29/76

CPC分类号： H01L29/94 ,  H01L21/823418 ,  H01L27/0629 ,  H01L27/105

摘要： A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first sidewall, a first drain region in the first region proximate to the second sidewall, an upper electrode on the second region and having a first sidewall and a second sidewall, a second source region in the second region proximate to the first sidewall of the upper electrode, and a second drain region in the second region proximate to the second sidewall of the upper electrode, wherein an impurity doping concentration of the first source region and the first drain region is greater than an impurity doping concentration of the second source region and the second drain region.

摘要翻译： 提供具有包括第一区域和第二区域的半导体衬底的半导体器件。 所述半导体器件还包括位于所述第一区域上并具有第一侧壁和第二侧壁的栅电极，所述第一区域中靠近所述第一侧壁的第一源极区域，所述第一区域中靠近所述第二侧壁的第一漏极区域， 在第二区域上的上电极，具有第一侧壁和第二侧壁，第二区域中靠近上电极的第一侧壁的第二区域，以及靠近第二侧壁的第二区域中的第二漏极区域 所述上电极，其中所述第一源极区域和所述第一漏极区域的杂质掺杂浓度大于所述第二源极区域和所述第二漏极区域的杂质掺杂浓度。