公开(公告)号：US20120314480A1

公开(公告)日：2012-12-13

申请号：US13490713

申请日：2012-06-07

申请人： Junya ONISHI ,  Nobuyoshi Awaya ,  Mitsuru Nakura ,  Kazuya Ishihara

发明人： Junya ONISHI ,  Nobuyoshi Awaya ,  Mitsuru Nakura ,  Kazuya Ishihara

IPC分类号： G11C11/00

CPC分类号： G06F11/1048 ,  G11C13/004 ,  G11C13/0061 ,  G11C2029/0411

摘要： In a semiconductor memory device using a variable resistive element made of a metal oxide for storing information, a voltage amplitude of a writing voltage pulse for changing the variable resistive element to a high resistance state is set within a voltage range in which the resistance value of the high resistance state after the change increases with time. The voltage amplitude is set within the voltage range in which the resistance value of the high resistance state after the change increases toward a predetermined peak with increase in voltage amplitude. When a data error is detected by the ECC circuit, it is estimated that the data that should be in the low resistance state changes to the high resistance state, and the variable resistive elements of all memory cells from which the error is detected are written to the low resistance state to correct the error bit.

摘要翻译： 在使用由金属氧化物制成的可变电阻元件用于存储信息的半导体存储器件中，将可变电阻元件改变为高电阻状态的写入电压脉冲的电压幅度设定在电阻值 变化后的高电阻状态随时间而增加。 电压幅度设定在电压范围内，随着电压振幅的增加，变化后的高电阻状态的电阻值向预定的峰值增加。 当ECC电路检测到数据错误时，估计应该处于低电阻状态的数据变为高电阻状态，并且将检测到错误的所有存储单元的可变电阻元件写入 低电阻状态来纠正错误位。

公开(公告)号：US20120075911A1

公开(公告)日：2012-03-29

申请号：US13224814

申请日：2011-09-02

申请人： Mitsuru NAKURA ,  Kazuya Ishihara ,  Shinobu Yamazaki ,  Suguru Kawabata

发明人： Mitsuru NAKURA ,  Kazuya Ishihara ,  Shinobu Yamazaki ,  Suguru Kawabata

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097

摘要： Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. Further, the memory cell array is constituted of even-numbers of subbanks, and the application of the erasing voltage pulse in one subbank and the application of the programming voltage pulse in the other subbank are alternately performed.

摘要翻译： 无论作为写入动作（擦除和编程动作）的目标的存储单元的可变电阻元件的电阻状态，将可变电阻元件的电阻状态变为最低的擦除状态的擦除电压脉冲 电阻值被应用。 此后，将用于使可变电阻元件的电阻状态变为期望编程状态的编程电压脉冲被施加到编程动作目标存储单元的可变电阻元件。 通过在施加擦除电压脉冲之后始终应用编程电压脉冲，可以避免顺序施加的多个编程电压脉冲。 此外，存储单元阵列由偶数个子库构成，并且将擦除电压脉冲应用于一个子库中，并且编程电压脉冲在另一个子库中的应用被交替执行。

公开(公告)号：US08514607B2

公开(公告)日：2013-08-20

申请号：US13212457

申请日：2011-08-18

申请人： Mitsuru Nakura ,  Kazuya Ishihara ,  Shinobu Yamazaki ,  Suguru Kawabata

发明人： Mitsuru Nakura ,  Kazuya Ishihara ,  Shinobu Yamazaki ,  Suguru Kawabata

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/79

摘要： Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided.

摘要翻译： 提供一种半导体存储器件，其能够在随机存取编程动作中以期望的可控制性稳定地编程到期望的电阻状态，并且具有可变电阻元件。 无论作为写入动作（擦除和编程动作）的目标的存储单元的可变电阻元件的电阻状态，将可变电阻元件的电阻状态变为最低的擦除状态的擦除电压脉冲 电阻值被应用。 此后，将用于使可变电阻元件的电阻状态变为期望编程状态的编程电压脉冲被施加到编程动作目标存储单元的可变电阻元件。 通过在施加擦除电压脉冲之后始终应用编程电压脉冲，可以避免顺序施加的多个编程电压脉冲。

公开(公告)号：US08482956B2

公开(公告)日：2013-07-09

申请号：US13179839

申请日：2011-07-11

申请人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

发明人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C7/1048 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路， 电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。 在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子， 并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

公开(公告)号：US08411487B2

公开(公告)日：2013-04-02

申请号：US13224814

申请日：2011-09-02

申请人： Mitsuru Nakura ,  Kazuya Ishihara ,  Shinobu Yamazaki ,  Suguru Kawabata

发明人： Mitsuru Nakura ,  Kazuya Ishihara ,  Shinobu Yamazaki ,  Suguru Kawabata

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097

摘要： Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. Further, the memory cell array is constituted of even-numbers of subbanks, and the application of the erasing voltage pulse in one subbank and the application of the programming voltage pulse in the other subbank are alternately performed.

摘要翻译： 无论作为写入动作（擦除和编程动作）的目标的存储单元的可变电阻元件的电阻状态，将可变电阻元件的电阻状态变为最低的擦除状态的擦除电压脉冲 电阻值被应用。 此后，将用于使可变电阻元件的电阻状态变为期望编程状态的编程电压脉冲被施加到编程动作目标存储单元的可变电阻元件。 通过在施加擦除电压脉冲之后始终应用编程电压脉冲，可以避免顺序施加的多个编程电压脉冲。 此外，存储单元阵列由偶数个子库构成，并且将擦除电压脉冲应用于一个子库中，并且编程电压脉冲在另一个子库中的应用被交替执行。

公开(公告)号：US20110292715A1

公开(公告)日：2011-12-01

申请号：US13114507

申请日：2011-05-24

申请人： Kazuya Ishihara ,  Mitsuru Nakura ,  Yoshiji Ohta

发明人： Kazuya Ishihara ,  Mitsuru Nakura ,  Yoshiji Ohta

IPC分类号： G11C11/00 ,  G11C7/12

CPC分类号： G11C7/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells is aligned in a matrix shape, each memory cell including a two-terminal memory element and a transistor for selection connected in series; a first voltage applying circuit that applies a writing voltage pulse to first bit lines; and a second voltage applying circuit that applies a pre-charge voltage to the first bit lines and second bit lines, wherein in a writing of a memory cell, after the second voltage applying circuit has pre-charged both ends of the memory cell to a same voltage, the first voltage applying circuit applies the writing voltage pulse via the first bit line that is directly connected to the transistor for selection, and the second voltage applying circuit applies the pre-charge voltage to the second bit line directly connected to the memory element.

摘要翻译： 半导体存储器件包括其中多个存储器单元以矩阵形状排列的存储单元阵列，每个存储单元包括串联连接的两端存储元件和选择晶体管; 对第一位线施加写入电压脉冲的第一电压施加电路; 以及施加预充电电压到第一位线和第二位线的第二电压施加电路，其中在存储单元的写入中，在所述第二电压施加电路将所述存储器单元的两端预充电到 第一电压施加电路经由直接连接到晶体管的第一位线施加写入电压脉冲用于选择，并且第二电压施加电路将预充电电压施加到直接连接到存储器的第二位线 元件。

公开(公告)号：US08560923B2

公开(公告)日：2013-10-15

申请号：US13416144

申请日：2012-03-09

申请人： Mitsuru Nakura ,  Nobuyoshi Awaya ,  Kazuya Ishihara

发明人： Mitsuru Nakura ,  Nobuyoshi Awaya ,  Kazuya Ishihara

IPC分类号： G11C29/00 ,  G11C7/10 ,  H01L29/06

CPC分类号： G11C13/0069 ,  G06F11/1048 ,  G11C13/0007 ,  G11C29/52 ,  G11C2013/0073 ,  G11C2029/0411

摘要： The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

摘要翻译： 本发明实现了可以有效地执行可能在连续读取动作中发生的数据错误的检测和错误数据的校正的半导体存储器件。 半导体存储器件使用由金属氧化物制成的可变电阻元件来存储信息。 在半导体存储器件中的具有ECC的编码数据的读取动作期间，当由ECC电路检测到数据错误时，将具有与读取电压脉冲的极性相反的极性的写入电压脉冲施加到来自 假设由于施加具有与所施加的读取电压脉冲的极性相同的极性的写入电压脉冲而发生错误写入的假设，检测出错误以便校正检测到错误的位。

公开(公告)号：US08508978B2

公开(公告)日：2013-08-13

申请号：US13114507

申请日：2011-05-24

申请人： Kazuya Ishihara ,  Mitsuru Nakura ,  Yoshiji Ohta

发明人： Kazuya Ishihara ,  Mitsuru Nakura ,  Yoshiji Ohta

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

摘要： A semiconductor memory device includes a memory cell array in which a plurality of memory cells is aligned in a matrix shape, each memory cell including a two-terminal memory element and a transistor for selection connected in series; a first voltage applying circuit that applies a writing voltage pulse to first bit lines; and a second voltage applying circuit that applies a pre-charge voltage to the first bit lines and second bit lines, wherein in a writing of a memory cell, after the second voltage applying circuit has pre-charged both ends of the memory cell to a same voltage, the first voltage applying circuit applies the writing voltage pulse via the first bit line that is directly connected to the transistor for selection, and the second voltage applying circuit applies the pre-charge voltage to the second bit line directly connected to the memory element.

摘要翻译： 半导体存储器件包括其中多个存储器单元以矩阵形状排列的存储单元阵列，每个存储单元包括串联连接的两端存储元件和选择晶体管; 对第一位线施加写入电压脉冲的第一电压施加电路; 以及施加预充电电压到第一位线和第二位线的第二电压施加电路，其中在存储单元的写入中，在所述第二电压施加电路将所述存储器单元的两端预充电到 第一电压施加电路经由直接连接到晶体管的第一位线施加写入电压脉冲用于选择，并且第二电压施加电路将预充电电压施加到直接连接到存储器的第二位线 元件。

公开(公告)号：US20120266043A1

公开(公告)日：2012-10-18

申请号：US13416144

申请日：2012-03-09

申请人： Mitsuru Nakura ,  Nobuyoshi Awaya ,  Kazuya Ishihara

发明人： Mitsuru Nakura ,  Nobuyoshi Awaya ,  Kazuya Ishihara

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G11C13/0069 ,  G06F11/1048 ,  G11C13/0007 ,  G11C29/52 ,  G11C2013/0073 ,  G11C2029/0411

摘要： The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

摘要翻译： 本发明实现了可以有效地执行可能在连续读取动作中发生的数据错误的检测和错误数据的校正的半导体存储器件。 半导体存储器件使用由金属氧化物制成的可变电阻元件来存储信息。 在半导体存储器件中的具有ECC的编码数据的读取动作期间，当由ECC电路检测到数据错误时，将具有与读取电压脉冲的极性相反的极性的写入电压脉冲施加到来自 假设由于施加具有与所施加的读取电压脉冲的极性相同的极性的写入电压脉冲而发生错误写入的假设，检测出错误以便校正检测到错误的位。

公开(公告)号：US20120014163A1

公开(公告)日：2012-01-19

申请号：US13179839

申请日：2011-07-11

申请人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

发明人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C7/1048 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路， 电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。 在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子， 并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。