公开(公告)号：US08482956B2

公开(公告)日：2013-07-09

申请号：US13179839

申请日：2011-07-11

申请人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

发明人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C7/1048 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路， 电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。 在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子， 并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

公开(公告)号：US20120014163A1

公开(公告)日：2012-01-19

申请号：US13179839

申请日：2011-07-11

申请人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

发明人： Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Mitsuru Nakura ,  Suguru Kawabata ,  Nobuyoshi Awaya

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C7/1048 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路， 电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。 在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子， 并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

公开(公告)号：US08422270B2

公开(公告)日：2013-04-16

申请号：US13044892

申请日：2011-03-10

申请人： Suguru Kawabata ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

发明人： Suguru Kawabata ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

IPC分类号： G11C11/34

CPC分类号： G11C13/004 ,  G11C2013/0045 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.

摘要翻译： 非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路， 每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。 每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线 或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

公开(公告)号：US20110228586A1

公开(公告)日：2011-09-22

申请号：US13044892

申请日：2011-03-10

申请人： Suguru KAWABATA ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

发明人： Suguru KAWABATA ,  Shinobu Yamazaki ,  Yoshiji Ohta ,  Kazuya Ishihara ,  Nobuyoshi Awaya ,  Akio Kitagawa ,  Kazuya Nakayama

IPC分类号： G11C11/34

CPC分类号： G11C13/004 ,  G11C2013/0045 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77

摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.

摘要翻译： 非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路， 每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。 每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线 或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

公开(公告)号：US08411488B2

公开(公告)日：2013-04-02

申请号：US13233301

申请日：2011-09-15

申请人： Suguru Kawabata ,  Shinobu Yamazaki ,  Kazuya Ishihara ,  Junya Onishi ,  Nobuyoshi Awaya ,  Yukio Tamai

发明人： Suguru Kawabata ,  Shinobu Yamazaki ,  Kazuya Ishihara ,  Junya Onishi ,  Nobuyoshi Awaya ,  Yukio Tamai

IPC分类号： G11C11/00

CPC分类号： G11C11/5685 ,  G11C13/0007 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/79

摘要： A nonvolatile semiconductor memory device includes a memory cell array for storing user data provided by arranging memory cells each having a variable resistive element having a first electrode, a second electrode, and a variable resistor made of a metal oxide sandwiched between the first and second electrodes. The first and second electrodes are formed of a conductive material forming ohmic junction with the variable resistor and a conductive material forming non-ohmic junction with the variable resistor, respectively. The variable resistor changes between two or more different resistance states by applying a voltage between the electrodes. The resistance state after being changed is maintained in a nonvolatile manner. The variable resistive elements of all memory cells in the memory cell array are set to the highest of the two or more different resistance states in an unused state before the memory cell array is used to store the user data.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列，用于存储通过布置存储单元而提供的用户数据，每个存储单元具有可变电阻元件，该可变电阻元件具有第一电极，第二电极和夹在第一和第二电极之间的金属氧化物制成的可变电阻器 。 第一和第二电极由与可变电阻器形成欧姆结的导电材料和分别与可变电阻器形成非欧姆结的导电材料形成。 可变电阻器通过在电极之间施加电压而在两个或多个不同的电阻状态之间变化。 改变后的电阻状态保持非挥发性。 在存储单元阵列用于存储用户数据之前，将存储单元阵列中的所有存储单元的可变电阻元件设置为处于未使用状态的两个或多个不同电阻状态中的最高值。

公开(公告)号：US08593855B2

公开(公告)日：2013-11-26

申请号：US13490713

申请日：2012-06-07

申请人： Junya Onishi ,  Nobuyoshi Awaya ,  Mitsuru Nakura ,  Kazuya Ishihara

发明人： Junya Onishi ,  Nobuyoshi Awaya ,  Mitsuru Nakura ,  Kazuya Ishihara

IPC分类号： G11C11/00

CPC分类号： G06F11/1048 ,  G11C13/004 ,  G11C13/0061 ,  G11C2029/0411

摘要： In a semiconductor memory device using a variable resistive element made of a metal oxide for storing information, a voltage amplitude of a writing voltage pulse for changing the variable resistive element to a high resistance state is set within a voltage range in which the resistance value of the high resistance state after the change increases with time. The voltage amplitude is set within the voltage range in which the resistance value of the high resistance state after the change increases toward a predetermined peak with increase in voltage amplitude. When a data error is detected by the ECC circuit, it is estimated that the data that should be in the low resistance state changes to the high resistance state, and the variable resistive elements of all memory cells from which the error is detected are written to the low resistance state to correct the error bit.

摘要翻译： 在使用由金属氧化物制成的可变电阻元件用于存储信息的半导体存储器件中，将可变电阻元件改变为高电阻状态的写入电压脉冲的电压幅度设定在电阻值 变化后的高电阻状态随时间而增加。 电压幅度设定在电压范围内，随着电压振幅的增加，变化后的高电阻状态的电阻值向预定的峰值增加。 当ECC电路检测到数据错误时，估计应该处于低电阻状态的数据变为高电阻状态，并且将检测到错误的所有存储单元的可变电阻元件写入 低电阻状态来纠正错误位。

公开(公告)号：US20120314480A1

公开(公告)日：2012-12-13

申请号：US13490713

申请日：2012-06-07

申请人： Junya ONISHI ,  Nobuyoshi Awaya ,  Mitsuru Nakura ,  Kazuya Ishihara

发明人： Junya ONISHI ,  Nobuyoshi Awaya ,  Mitsuru Nakura ,  Kazuya Ishihara

IPC分类号： G11C11/00

CPC分类号： G06F11/1048 ,  G11C13/004 ,  G11C13/0061 ,  G11C2029/0411

摘要： In a semiconductor memory device using a variable resistive element made of a metal oxide for storing information, a voltage amplitude of a writing voltage pulse for changing the variable resistive element to a high resistance state is set within a voltage range in which the resistance value of the high resistance state after the change increases with time. The voltage amplitude is set within the voltage range in which the resistance value of the high resistance state after the change increases toward a predetermined peak with increase in voltage amplitude. When a data error is detected by the ECC circuit, it is estimated that the data that should be in the low resistance state changes to the high resistance state, and the variable resistive elements of all memory cells from which the error is detected are written to the low resistance state to correct the error bit.

摘要翻译： 在使用由金属氧化物制成的可变电阻元件用于存储信息的半导体存储器件中，将可变电阻元件改变为高电阻状态的写入电压脉冲的电压幅度设定在电阻值 变化后的高电阻状态随时间而增加。 电压幅度设定在电压范围内，随着电压振幅的增加，变化后的高电阻状态的电阻值向预定的峰值增加。 当ECC电路检测到数据错误时，估计应该处于低电阻状态的数据变为高电阻状态，并且将检测到错误的所有存储单元的可变电阻元件写入 低电阻状态来纠正错误位。

公开(公告)号：US08560923B2

公开(公告)日：2013-10-15

申请号：US13416144

申请日：2012-03-09

申请人： Mitsuru Nakura ,  Nobuyoshi Awaya ,  Kazuya Ishihara

发明人： Mitsuru Nakura ,  Nobuyoshi Awaya ,  Kazuya Ishihara

IPC分类号： G11C29/00 ,  G11C7/10 ,  H01L29/06

CPC分类号： G11C13/0069 ,  G06F11/1048 ,  G11C13/0007 ,  G11C29/52 ,  G11C2013/0073 ,  G11C2029/0411

摘要： The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

摘要翻译： 本发明实现了可以有效地执行可能在连续读取动作中发生的数据错误的检测和错误数据的校正的半导体存储器件。 半导体存储器件使用由金属氧化物制成的可变电阻元件来存储信息。 在半导体存储器件中的具有ECC的编码数据的读取动作期间，当由ECC电路检测到数据错误时，将具有与读取电压脉冲的极性相反的极性的写入电压脉冲施加到来自 假设由于施加具有与所施加的读取电压脉冲的极性相同的极性的写入电压脉冲而发生错误写入的假设，检测出错误以便校正检测到错误的位。

公开(公告)号：US20120266043A1

公开(公告)日：2012-10-18

申请号：US13416144

申请日：2012-03-09

申请人： Mitsuru Nakura ,  Nobuyoshi Awaya ,  Kazuya Ishihara

发明人： Mitsuru Nakura ,  Nobuyoshi Awaya ,  Kazuya Ishihara

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G11C13/0069 ,  G06F11/1048 ,  G11C13/0007 ,  G11C29/52 ,  G11C2013/0073 ,  G11C2029/0411

摘要： The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

摘要翻译： 本发明实现了可以有效地执行可能在连续读取动作中发生的数据错误的检测和错误数据的校正的半导体存储器件。 半导体存储器件使用由金属氧化物制成的可变电阻元件来存储信息。 在半导体存储器件中的具有ECC的编码数据的读取动作期间，当由ECC电路检测到数据错误时，将具有与读取电压脉冲的极性相反的极性的写入电压脉冲施加到来自 假设由于施加具有与所施加的读取电压脉冲的极性相同的极性的写入电压脉冲而发生错误写入的假设，检测出错误以便校正检测到错误的位。

公开(公告)号：US20120025163A1

公开(公告)日：2012-02-02

申请号：US13182696

申请日：2011-07-14

申请人： Junya ONISHI ,  Shinobu Yamazaki ,  Kazuya Ishihara ,  Yushi Inoue ,  Yukio Tamai ,  Nobuyoshi Awaya

发明人： Junya ONISHI ,  Shinobu Yamazaki ,  Kazuya Ishihara ,  Yushi Inoue ,  Yukio Tamai ,  Nobuyoshi Awaya

IPC分类号： H01L45/00

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146

摘要： A variable resistance element that can stably perform a switching operation with a property variation being reduced by suppressing a sharp current that accompanies completion of forming process, and a non-volatile semiconductor memory device including the variable resistance element are realized. The non-volatile semiconductor memory device uses the variable resistance element for storing information in which a resistance changing layer is interposed between a first electrode and a second electrode, and a buffer layer is inserted between the first electrode and the resistance changing layer where a switching interface is formed. The buffer layer and the resistance changing layer include n-type metal oxides, and materials of the buffer layer and the resistance changing layer are selected such that energy at a bottom of a conduction band of the n-type metal oxide configuring the buffer layer is lower than that of the n-type metal oxide configuring the resistance changing layer.

摘要翻译： 通过抑制伴随着成形处理的完成的尖锐电流，可以稳定地进行具有特性变化的开关动作的可变电阻元件，以及包括该可变电阻元件的非易失性半导体存储器件。 非易失性半导体存储器件使用可变电阻元件来存储在第一电极和第二电极之间插入电阻变化层的信息，并且缓冲层插入在第一电极和电阻变化层之间，其中开关 界面形成。 缓冲层和电阻变化层包括n型金属氧化物，并且选择缓冲层和电阻变化层的材料，使得构成缓冲层的n型金属氧化物的导带的底部的能量为 低于构成电阻变化层的n型金属氧化物。